with rgmii1_pins not specified by switch
in stock
# switch dump
hash port(0:6) fid vid age mac-address filter my_mac
found the last entry 0 (not ready)
# switch phy
SPEC defined Register
[Port 0]===============
00: 1000 01: 7949 02: 004D 03: D036 04: 0DE1 05: 0000 06: 0004 07: 2801
08: 0000 09: 0200 10: 0000 11: 0000 12: 0000 13: 0000 14: 0000 15: 2000
[Port 1]===============
00: 3100 01: 7949 02: 004D 03: D036 04: 0DE1 05: 0000 06: 0004 07: 2801
08: 0000 09: 0200 10: 0000 11: 0000 12: 0000 13: 0000 14: 0000 15: 2000
[Port 2]===============
00: 3100 01: 7949 02: 004D 03: D036 04: 0DE1 05: 0000 06: 0004 07: 2801
08: 0000 09: 0200 10: 0000 11: 0000 12: 0000 13: 0000 14: 0000 15: 2000
[Port 3]===============
00: 3100 01: 7949 02: 004D 03: D036 04: 0DE1 05: 0000 06: 0004 07: 2801
08: 0000 09: 0200 10: 0000 11: 0000 12: 0000 13: 0000 14: 0000 15: 2000
[Port 4]===============
00: 3100 01: 796D 02: 004D 03: D036 04: 0DE1 05: 51E1 06: 0007 07: 2001
08: 0000 09: 0200 10: 0000 11: 0000 12: 0000 13: 0000 14: 0000 15: 2000
Global Register Page 0
===============
16: 0862 17: 0050 18: 0000 19: 0000 20: 082C 21: 0000 22: 2400 23: 0000
24: 3200 25: 1000 26: 0000 27: 0000 28: 0000 29: 0000 30: 02EE 31: 0000
Global Register Page 1
===============
16: 0862 17: 0050 18: 0000 19: 0000 20: 082C 21: 0000 22: 2400 23: 0000
24: 3200 25: 1000 26: 0000 27: 0000 28: 0000 29: 0000 30: 02EE 31: 0000
Global Register Page 2
===============
16: 0862 17: 0050 18: 0000 19: 0000 20: 082C 21: 0000 22: 2400 23: 0000
24: 3200 25: 1000 26: 0000 27: 0000 28: 0000 29: 0000 30: 02EE 31: 0000
Global Register Page 3
===============
16: 0862 17: 0050 18: 0000 19: 0000 20: 082C 21: 0000 22: 2400 23: 0000
24: 3200 25: 1000 26: 0000 27: 0000 28: 0000 29: 0000 30: 02EE 31: 0000
Global Register Page 4
===============
16: 0862 17: 0050 18: 0000 19: 0000 20: 082C 21: 0000 22: 2400 23: 0000
24: 3200 25: 1000 26: 0000 27: 0000 28: 0000 29: 0000 30: 02EE 31: 0000
Local Register Port 0 Page 0
===============
16: 0862 17: 0010 18: 0000 19: 0000 20: 082C 21: 0000 22: 2400 23: 0000
24: 3200 25: 1000 26: 0000 27: 0000 28: 0000 29: 0000 30: 02EE 31: 0000
Local Register Port 0 Page 1
===============
16: 0862 17: 0010 18: 0000 19: 0000 20: 082C 21: 0000 22: 2400 23: 0000
24: 3200 25: 1000 26: 0000 27: 0000 28: 0000 29: 0000 30: 02EE 31: 0000
Local Register Port 0 Page 2
===============
16: 0862 17: 0010 18: 0000 19: 0000 20: 082C 21: 0000 22: 2400 23: 0000
24: 3200 25: 1000 26: 0000 27: 0000 28: 0000 29: 0000 30: 02EE 31: 0000
Local Register Port 0 Page 3
===============
16: 0862 17: 0010 18: 0000 19: 0000 20: 082C 21: 0000 22: 2400 23: 0000
24: 3200 25: 1000 26: 0000 27: 0000 28: 0000 29: 0000 30: 02EE 31: 0000
Local Register Port 1 Page 0
===============
16: 0862 17: 0050 18: 0000 19: 0000 20: 082C 21: 0000 22: 2400 23: 0000
24: 3200 25: 1000 26: 0000 27: 0000 28: 0000 29: 0000 30: 02EE 31: 0000
Local Register Port 1 Page 1
===============
16: 0862 17: 0050 18: 0000 19: 0000 20: 082C 21: 0000 22: 2400 23: 0000
24: 3200 25: 1000 26: 0000 27: 0000 28: 0000 29: 0000 30: 02EE 31: 0000
Local Register Port 1 Page 2
===============
16: 0862 17: 0050 18: 0000 19: 0000 20: 082C 21: 0000 22: 2400 23: 0000
24: 3200 25: 1000 26: 0000 27: 0000 28: 0000 29: 0000 30: 02EE 31: 0000
Local Register Port 1 Page 3
===============
16: 0862 17: 0050 18: 0000 19: 0000 20: 082C 21: 0000 22: 2400 23: 0000
24: 3200 25: 1000 26: 0000 27: 0000 28: 0000 29: 0000 30: 02EE 31: 0000
Local Register Port 2 Page 0
===============
16: 0862 17: 0050 18: 0000 19: 0000 20: 082C 21: 0000 22: 2400 23: 0000
24: 3200 25: 1000 26: 0000 27: 0000 28: 0000 29: 0000 30: 02EE 31: 0000
Local Register Port 2 Page 1
===============
16: 0862 17: 0050 18: 0000 19: 0000 20: 082C 21: 0000 22: 2400 23: 0000
24: 3200 25: 1000 26: 0000 27: 0000 28: 0000 29: 0000 30: 02EE 31: 0000
Local Register Port 2 Page 2
===============
16: 0862 17: 0050 18: 0000 19: 0000 20: 082C 21: 0000 22: 2400 23: 0000
24: 3200 25: 1000 26: 0000 27: 0000 28: 0000 29: 0000 30: 02EE 31: 0000
Local Register Port 2 Page 3
===============
16: 0862 17: 0050 18: 0000 19: 0000 20: 082C 21: 0000 22: 2400 23: 0000
24: 3200 25: 1000 26: 0000 27: 0000 28: 0000 29: 0000 30: 02EE 31: 0000
Local Register Port 3 Page 0
===============
16: 0862 17: 0010 18: 0000 19: 0000 20: 082C 21: 0000 22: 2400 23: 0000
24: 3200 25: 1000 26: 0000 27: 0000 28: 0000 29: 0000 30: 02EE 31: 0000
Local Register Port 3 Page 1
===============
16: 0862 17: 0010 18: 0000 19: 0000 20: 082C 21: 0000 22: 2400 23: 0000
24: 3200 25: 1000 26: 0000 27: 0000 28: 0000 29: 0000 30: 02EE 31: 0000
Local Register Port 3 Page 2
===============
16: 0862 17: 0010 18: 0000 19: 0000 20: 082C 21: 0000 22: 2400 23: 0000
24: 3200 25: 1000 26: 0000 27: 0000 28: 0000 29: 0000 30: 02EE 31: 0000
Local Register Port 3 Page 3
===============
16: 0862 17: 0010 18: 0000 19: 0000 20: 082C 21: 0000 22: 2400 23: 0000
24: 3200 25: 1000 26: 0000 27: 0000 28: 0000 29: 0000 30: 02EE 31: 0000
Local Register Port 4 Page 0
===============
16: 0862 17: 7C10 18: 0000 19: 7400 20: 082C 21: 0000 22: 2400 23: 0000
24: 3200 25: 1000 26: 0000 27: 0000 28: 0000 29: 0000 30: 02EE 31: 0000
Local Register Port 4 Page 1
===============
16: 0862 17: 7C10 18: 0000 19: 0000 20: 082C 21: 0000 22: 2400 23: 0000
24: 3200 25: 1000 26: 0000 27: 0000 28: 0000 29: 0000 30: 02EE 31: 0000
Local Register Port 4 Page 2
===============
16: 0862 17: 7C10 18: 0000 19: 0000 20: 082C 21: 0000 22: 2400 23: 0000
24: 3200 25: 1000 26: 0000 27: 0000 28: 0000 29: 0000 30: 02EE 31: 0000
Local Register Port 4 Page 3
===============
16: 0862 17: 7C10 18: 0000 19: 0000 20: 082C 21: 0000 22: 2400 23: 0000
24: 3200 25: 1000 26: 0000 27: 0000 28: 0000 29: 0000 30: 02EE 31: 0000
#
.
# cat proc/mt7620/gmac
FE_INT_ENABLE : 0x0003000f
DLY_INT_CFG : 0x00000000
TX_BASE_PTR0 : 0x03f74000
TX_CTX_IDX0 : 0x00000059
TX_DTX_IDX0 : 0x00000059
TX_BASE_PTR1(0xb0100810) : 0x00000000
TX_CTX_IDX1(0xb0100818) : 0x00000000
TX_DTX_IDX1(0xb010081c) : 0x00000000
TX_BASE_PTR2(0xb0100820) : 0x00000000
TX_CTX_IDX2(0xb0100828) : 0x00000000
TX_DTX_IDX2(0xb010082c) : 0x00000000
TX_BASE_PTR3(0xb0100830) : 0x00000000
TX_CTX_IDX3(0xb0100838) : 0x00000000
TX_DTX_IDX3(0xb010083c) : 0x00000000
RX_BASE_PTR0 : 0x03f75000# cat proc/mt7620/esw_cnt
<<CPU>>
|
+-----------------------------------------------+
| <<PSE>> |
+-----------------------------------------------+
|
+-----------------------------------------------+
| <<GDMA>> |
| GDMA1_TX_GPCNT : 0000000092 (Tx Good Pkts) |
| GDMA1_RX_GPCNT : 0000000065 (Rx Good Pkts) |
| |
| GDMA1_TX_SKIPCNT: 0000000000 (skip) |
| GDMA1_TX_COLCNT : 0000000000 (collision) |
| GDMA1_RX_OERCNT : 0000000000 (overflow) |
| GDMA1_RX_FERCNT : 0000000000 (FCS error) |
| GDMA1_RX_SERCNT : 0000000000 (too short) |
| GDMA1_RX_LERCNT : 0000000000 (too long) |
| GDMA1_RX_CERCNT : 0000000000 (l3/l4 checksum) |
| GDMA1_RX_FCCNT : 0000000000 (flow control) |
| |
| GDMA2_TX_GPCNT : 0000000017 (Tx Good Pkts) |
| GDMA2_RX_GPCNT : 0000000017 (Rx Good Pkts) |
| |
| GDMA2_TX_SKIPCNT: 0000000000 (skip) |
| GDMA2_TX_COLCNT : 0000000000 (collision) |
| GDMA2_RX_OERCNT : 0000000000 (overflow) |
| GDMA2_RX_FERCNT : 0000000000 (FCS error) |
| GDMA2_RX_SERCNT : 0000000000 (too short) |
| GDMA2_RX_LERCNT : 0000000000 (too long) |
| GDMA2_RX_CERCNT : 0043293200 (l3/l4 checksum) |
| GDMA2_RX_FCCNT : 0268748582 (flow control) |
+-----------------------------------------------+
^
| Port6 Rx:00000094 Good Pkt
| Port6 Rx:00000000 Bad Pkt
| Port6 Tx:00000065 Good Pkt
| Port6 Tx:00000000 Bad Pkt
| Port7 Rx:00000017 Good Pkt
| Port7 Rx:00000000 Bad Pkt
| Port7 Tx:00000017 Good Pkt
| Port7 Tx:00000000 Bad Pkt
+---------------------v-------------------------+
| P6 |
| <<10/100/1000 Embedded Switch>> |
| P0 P1 P2 P3 P4 P5 |
+-----------------------------------------------+
| | | | | |
Port0 Good RX=00000000 Tx=00000000 (Bad Rx=00000000 Tx=00000000)
Port1 Good RX=00000000 Tx=00000000 (Bad Rx=00000000 Tx=00000000)
Port2 Good RX=00000000 Tx=00000000 (Bad Rx=00000000 Tx=00000000)
Port3 Good RX=00000000 Tx=00000000 (Bad Rx=00000000 Tx=00000000)
Port4 Good RX=00000000 Tx=00000000 (Bad Rx=00000000 Tx=00000000)
Port5 Good RX=00000065 Tx=00000094 (Bad Rx=00000000 Tx=00000000)
#
RX_MAX_CNT0 : 0x00000100
RX_CALC_IDX0 : 0x0000003a
RX_DRX_IDX0 : 0x0000003b
#
.
# vi /usr/etc/svn.list
svn://svn.atc.amit.com.tw/Mascot/RT305XL/branches/SI_trunk -r 15532
svn://svn.atc.amit.com.tw/Gobi/jboot/trunk -r 695
svn://svn.atc.amit.com.tw/Sahara/Ralink_SDK4.0.0.0/trunk/linux-2.6.36.x -r 342
svn://svn.atc.amit.com.tw/Sahara/OasisHeader/trunk -r 2182
svn://svn.atc.amit.com.tw/Gobi/CornerHeader/trunk -r 36
svn://svn.atc.amit.com.tw/Gobi/AmitUpgBuf/trunk -r 101
svn://svn.atc.amit.com.tw/Gobi/CSMan/trunk -r 144
svn://svn.atc.amit.com.tw/Gobi/GetPsec/trunk -r 29
svn://svn.atc.amit.com.tw/Gobi/Uyghur/trunk -r 109
svn://svn.atc.amit.com.tw/Gobi/WSL/WS-BAKSET/trunk -r 331
svn://svn.atc.amit.com.tw/Gobi/WSL/WS-DAS/trunk -r 251
svn://svn.atc.amit.com.tw/Gobi/WSL/WS-ESP/trunk -r 310
svn://svn.atc.amit.com.tw/Gobi/WSL/WS-FLUPL/trunk -r 332
svn://svn.atc.amit.com.tw/Gobi/WSL/WS-FWUPG/trunk -r 311
svn://svn.atc.amit.com.tw/Gobi/WSL/WS-UIR/trunk -r 318
svn://svn.atc.amit.com.tw/Sahara/Siwa/SyncDate/branches/94526 -r 56
svn://svn.atc.amit.com.tw/Gobi/AMIT_BEID/trunk -r 37
svn://svn.atc.amit.com.tw/Gobi/ConntrackViewer/trunk -r 17
svn://svn.atc.amit.com.tw/Gobi/OMailtool/trunk -r 59
svn://svn.atc.amit.com.tw/Gobi/RalinkAppGPIO/trunk -r 39
svn://svn.atc.amit.com.tw/Gobi/RalinkMiiMgr/trunk -r 3
svn://svn.atc.amit.com.tw/Gobi/RlogAlert/trunk -r 41
svn://svn.atc.amit.com.tw/Gobi/RlogReader/trunk -r 34
- /usr/etc/svn.list [Read-only] 1/167 0%
# mii_mgr -g -p 1 -r 1
phy 1, reg 1, val 0x7949
Get: phy[1].reg[1] = 7949
# mii_mgr -g -p 0 -r 0
phy 0, reg 0, val 0x1000
Get: phy[0].reg[0] = 1000
# mii_mgr -g -p 1 -r 0
phy 1, reg 0, val 0x3100
Get: phy[1].reg[0] = 3100
# mii_mgr -g -p 2 -r 0
phy 2, reg 0, val 0x3100
Get: phy[2].reg[0] = 3100
# mii_mgr -g -p 3 -r 0
phy 3, reg 0, val 0x3100
Get: phy[3].reg[0] = 3100
# mii_mgr -g -p 4 -r 0
phy 4, reg 0, val 0x3100
Get: phy[4].reg[0] = 3100
# mii_mgr -g -p 5 -r 0
phy 5, reg 0, val 0xffff
Get: phy[5].reg[0] = ffff
# mii_mgr -g -p 6 -r 0
phy 6, reg 0, val 0xffff
Get: phy[6].reg[0] = ffff
# mii_mgr -g -p 0 -r 1
phy 0, reg 1, val 0x7949
Get: phy[0].reg[1] = 7949
# mii_mgr -g -p 0 -r 2
phy 0, reg 2, val 0x4d
Get: phy[0].reg[2] = 004d
# mii_mgr -g -p 0 -r 3
phy 0, reg 3, val 0xd036
Get: phy[0].reg[3] = d036
# mii_mgr -g -p 0 -r 4
phy 0, reg 4, val 0xde1
Get: phy[0].reg[4] = 0de1
# mii_mgr -g -p 0 -r 5
phy 0, reg 5, val 0x0
Get: phy[0].reg[5] = 0000
# mii_mgr -g -p 0 -r 6
phy 0, reg 6, val 0x4
Get: phy[0].reg[6] = 0004
# mii_mgr -g -p 0 -r 0
phy 0, reg 0, val 0x1000
Get: phy[0].reg[0] = 1000
can have someone else going as to how to edit mdio-bus registers on an uninstalled system ?
I found a clone of my device TW-LTE4G3G-REITITIN
https://www.telewell.fi/fi/tuote/tuotannosta-poistuneet-tuotteet/wlan-tuotteet/TW-LTE4G3G-REITITIN/tw-lte4g3g-reititin
# switch reg r 0x0
switch reg read offset=0, value=0
# switch reg r 0x4d
switch reg read offset=4d, value=a01b5811
# switch reg r 0x036d
switch reg read offset=36d, value=0
# switch reg r 0x0004
switch reg read offset=4, value=f
# switch reg r 0x000c
switch reg read offset=c, value=71819
# switch reg r 0x00c
switch reg read offset=c, value=71819
# switch reg r 0x008
switch reg read offset=8, value=0
# switch reg r 0x010
switch reg read offset=10, value=7f7f7fe0
# switch reg r 0x010
switch reg read offset=10, value=7f7f7fe0
# i
ichecksum igmpproxy ip2hex ipheth-pair
ieee8021x-action init ip2net iptables
ifconfig insmod ip6tables iwconfig
igmp-action ip ipheth-action iwpriv
# ip
ip ip2net ipheth-action iptables
ip2hex ip6tables ipheth-pair
# ip
Usage: ip [ OPTIONS ] OBJECT { COMMAND | help }
where OBJECT := { link | addr | route | rule | neigh | tunnel |
maddr | mroute | monitor | xfrm }
OPTIONS := { -V[ersion] | -s[tatistics] | -r[esolve] |
-f[amily] { inet | inet6 | ipx | dnet | link } | -o[neline]
# ip show
Object "show" is unknown, try "ip help".
# sw
swapoff swapon switch
# switch
Usage:
switch acl etype add [ethtype] [portmap] - drop etherytype packets
switch acl dip add [dip] [portmap] - drop dip packets
switch acl dip meter [dip] [portmap][meter:kbps] - rate limit dip packets
switch acl dip trtcm [dip] [portmap][CIR:kbps][CBS][PIR][PBS] - TrTCM dip packe ts
switch acl port add [sport] [portmap] - drop src port packets
switch acl L4 add [2byes] [portmap] - drop L4 packets with 2bytes p ayload
switch add [mac] [portmap] - add an entry to switch table
switch add [mac] [portmap] [vlan id] - add an entry to switch table
switch add [mac] [portmap] [vlan id] [age] - add an entry to switch table
switch clear - clear switch table
switch del [mac] - delete an entry from switch table
switch del [mac] [fid] - delete an entry from switch table
switch dip add [dip] [portmap] - add a dip entry to switch tab le
switch dip del [dip] - del a dip entry to switch table
switch dip dump - dump switch dip table
switch dip clear - clear switch dip table
switch dump - dump switch table
switch ingress-rate on [port] [Mbps] - set ingress rate limit on port 0~ 4
switch egress-rate on [port] [Mbps] - set egress rate limit on port 0~4
switch ingress-rate off [port] - del ingress rate limit on port 0~ 4
switch egress-rate off [port] - del egress rate limit on port 0~4
switch filt [mac] - add a SA filtering entry (with po rtmap 1111111) to switch table
switch filt [mac] [portmap] - add a SA filtering entry to switc h table
switch filt [mac] [portmap] [vlan id] - add a SA filtering entry to switc h table
switch filt [mac] [portmap] [vlan id] [age] - add a SA filtering entry to switc h table
switch mymac [mac] [portmap] - add a mymac entry to switch tab le
switch mirror monitor [portnumber] - enable port mirror and indicate monitor port number
switch mirror target [portnumber] [0:off, 1:rx, 2:tx, 3:all] - set port mirror target
switch phy [phy_addr] - dump phy register of specific port
switch phy - dump all phy registers
switch reg r [offset] - register read from offset
switch reg w [offset] [value] - register write value to offset
switch sip add [sip] [dip] [portmap] - add a sip entry to switch tab le
switch sip del [sip] [dip] - del a sip entry to switch table
switch sip dump - dump switch sip table
switch sip clear - clear switch sip table
switch vlan dump - dump switch table
switch vlan set [vlan idx] [vid] [portmap] - set vlan id and associated member
switch reg athr_r [offset] - athr_register read from offset
switch reg athr_w [offset] [value] - athr_register write value to offse t
# switch reg athr_r 0x0000
read athero reg off:0 val:1302
switch reg read_athr offset=0, value=1302
# switch reg athr_r 0x0004
read athero reg off:4 val:87300000
switch reg read_athr offset=4, value=87300000
# switch reg athr_r 0x0008
read athero reg off:8 val:1000000
switch reg read_athr offset=8, value=1000000
# switch reg athr_r 0x000c
read athero reg off:c val:0
switch reg read_athr offset=c, value=0
# switch reg athr_r 0x00010
read athero reg off:10 val:40000000
switch reg read_athr offset=10, value=40000000
# switch reg athr_r 0x00020
read athero reg off:20 val:3f100a02
switch reg read_athr offset=20, value=3f100a02
# switch reg athr_r 0x00024
read athero reg off:24 val:10000
switch reg read_athr offset=24, value=10000
# switch reg athr_r 0x00028
read athero reg off:28 val:0
switch reg read_athr offset=28, value=0
# switch reg athr_r 0x0002c
read athero reg off:2c val:0
switch reg read_athr offset=2c, value=0
# switch reg athr_r 0x00030
read athero reg off:30 val:80000700
switch reg read_athr offset=30, value=80000700
# switch reg athr_r 0x00034
read athero reg off:34 val:0
switch reg read_athr offset=34, value=0
# switch reg athr_r 0x00038
read athero reg off:38 val:f000000
switch reg read_athr offset=38, value=f000000
# switch reg athr_r 0x0003c
read athero reg off:3c val:0
switch reg read_athr offset=3c, value=0
# switch reg athr_r 0x00040
read athero reg off:40 val:700000
switch reg read_athr offset=40, value=700000
# switch reg athr_r 0x00044
read athero reg off:44 val:0
switch reg read_athr offset=44, value=0
# switch reg athr_r 0x00048
read athero reg off:48 val:28100
switch reg read_athr offset=48, value=28100
# switch reg athr_r 0x00050
read athero reg off:50 val:cc35cc35
switch reg read_athr offset=50, value=cc35cc35
# switch reg athr_r 0x00054
read athero reg off:54 val:ca35ca35
switch reg read_athr offset=54, value=ca35ca35
# switch reg athr_r 0x00058
read athero reg off:58 val:c935c935
switch reg read_athr offset=58, value=c935c935
# switch reg athr_r 0x0005c
read athero reg off:5c val:3ffff00
switch reg read_athr offset=5c, value=3ffff00
# switch reg athr_r 0x00060
read athero reg off:60 val:1
switch reg read_athr offset=60, value=1
# switch reg athr_r 0x00064
read athero reg off:64 val:0
switch reg read_athr offset=64, value=0
# switch reg athr_r 0x00078
read athero reg off:78 val:5f2
switch reg read_athr offset=78, value=5f2
# switch reg athr_r 0x0007c
read athero reg off:7c val:7e
switch reg read_athr offset=7c, value=7e
# switch reg athr_r 0x00080
read athero reg off:80 val:2b0
switch reg read_athr offset=80, value=2b0
# switch reg athr_r 0x00084
read athero reg off:84 val:2b0
switch reg read_athr offset=84, value=2b0
# switch reg athr_r 0x00090
read athero reg off:90 val:2b0
switch reg read_athr offset=90, value=2b0
# switch reg athr_r 0x0009c
read athero reg off:9c val:0
switch reg read_athr offset=9c, value=0
# switch reg athr_r 0x00094
read athero reg off:94 val:1080
switch reg read_athr offset=94, value=1080
# switch reg athr_r 0x000a9
read athero reg off:a9 val:0
switch reg read_athr offset=a9, value=0
# switch reg athr_r 0x000a0
read athero reg off:a0 val:0
switch reg read_athr offset=a0, value=0
# switch reg athr_r 0x000a4
read athero reg off:a4 val:0
switch reg read_athr offset=a4, value=0
# switch reg athr_r 0x000a8
read athero reg off:a8 val:0
switch reg read_athr offset=a8, value=0
# switch reg athr_r 0x000ac
read athero reg off:ac val:0
switch reg read_athr offset=ac, value=0
# switch reg athr_r 0x000b0
read athero reg off:b0 val:0
switch reg read_athr offset=b0, value=0
# switch reg athr_r 0x000b4
read athero reg off:b4 val:0
switch reg read_athr offset=b4, value=0
# switch reg athr_r 0x000e0
read athero reg off:e0 val:c70164c0
switch reg read_athr offset=e0, value=c70164c0
# switch reg athr_r 0x00
read athero reg off:0 val:1302
switch reg read_athr offset=0, value=1302
# switch reg athr_r 0x01
read athero reg off:1 val:1302
switch reg read_athr offset=1, value=1302
# switch reg athr_r 0x02
read athero reg off:2 val:1302
switch reg read_athr offset=2, value=1302
# switch reg athr_r 0x0d01
read athero reg off:d01 val:0
switch reg read_athr offset=d01, value=0
# switch reg athr_r 0x0d02
read athero reg off:d02 val:0
switch reg read_athr offset=d02, value=0
# switch reg athr_r 0x0d03
read athero reg off:d03 val:0
switch reg read_athr offset=d03, value=0
# switch reg athr_r 0x0d04
read athero reg off:d04 val:0
switch reg read_athr offset=d04, value=0
# switch reg athr_r 0x0d05
read athero reg off:d05 val:0
switch reg read_athr offset=d05, value=0
# switch reg athr_r 0x0d06
read athero reg off:d06 val:0
switch reg read_athr offset=d06, value=0
# switch reg athr_r 0d06
read athero reg off:d06 val:0
switch reg read_athr offset=d06, value=0
# switch reg athr_r 0d01
read athero reg off:d01 val:0
switch reg read_athr offset=d01, value=0
# switch reg athr_r 0x0a
read athero reg off:a val:1000000
switch reg read_athr offset=a, value=1000000
# switch reg athr_r 0x0
read athero reg off:0 val:1302
switch reg read_athr offset=0, value=1302
# switch reg r 0x2004
switch reg read offset=2004, value=ff0000
# switch reg r 0x2000
switch reg read offset=2000, value=ffff
# switch reg r 0x2204
switch reg read offset=2204, value=ff0000
# switch reg r 0x2404
switch reg read offset=2404, value=ff0000
# switch reg r 0x2304
switch reg read offset=2304, value=ff0000
# switch reg r 0x2604
switch reg read offset=2604, value=c00001
# switch reg r 0x2704
switch reg read offset=2704, value=c00001
# switch reg r 0x3000
switch reg read offset=3000, value=56330
# switch reg r 0x3100
switch reg read offset=3100, value=56330
# switch reg r 0x3200
switch reg read offset=3200, value=56330
# switch reg r 0x3300
switch reg read offset=3300, value=56330
# switch reg r 0x3400
switch reg read offset=3400, value=56330
# switch reg r 0x3500
switch reg read offset=3500, value=5e33b
# switch reg r 0x3600
switch reg read offset=3600, value=5e33b
# switch reg r 0x3700
switch reg read offset=3700, value=5e33b
# switch reg r 0x3fe0
switch reg read offset=3fe0, value=3f25
# switch reg r 0x3fe4
switch reg read offset=3fe4, value=432880f1
# switch reg r 0x3fe8
switch reg read offset=3fe8, value=c
# switch reg r 0x3fe0
switch reg read offset=3fe0, value=3f25
# swttch reg r 0x3ff0
switch reg read offset=3ff0, value=1e03
# switch reg r 0x3ff4
switch reg read offset=3ff4, value=0
# switch reg r 0x3ff5
switch reg read offset=3ff5, value=0
# switch reg r 0x3ff4
switch reg read offset=3ff4, value=0
# switch reg r 0x3ff8
switch reg read offset=3ff8, value=0
# switch reg r 0x3ff0
switch reg read offset=3ff0, value=1e03
# switch reg r 0x3fe4
switch reg read offset=3fe4, value=432880f1
# switch reg r 0x3fe0
switch reg read offset=3fe0, value=3f25
# switch reg r 0x4800
switch reg read offset=4800, value=ff000f00
# switch reg r 0x7010
switch reg read offset=7010, value=883e0c00
# switch reg r 0x7014
switch reg read offset=7014, value=70008
# switch reg r 0x701c
switch reg read offset=701c, value=800000c
# switch reg r 0x8000
switch reg read offset=8000, value=b00002e
# switch reg r 0x8004
switch reg read offset=8004, value=0
# switch reg r 0x8000
switch reg read offset=8000, value=b00002e
# switch reg r 0x30e0
switch reg read offset=30e0, value=0
# switch reg r 0x58
switch reg read offset=58, value=9000000
# switch reg r 0x60
switch reg read offset=60, value=1b6db492
# switch reg r 0x4000
switch reg read offset=4000, value=0
# switch reg r 0x3fe8
switch reg read offset=3fe8, value=c
# switch reg r 0x3fe4
switch reg read offset=3fe4, value=432880f1
# switch reg r 0x3fff
switch reg read offset=3fff, value=0
# switch reg r 0x100
switch reg read offset=100, value=1002
# switch reg r 0x200
switch reg read offset=200, value=0
# switch reg r 0x7000
switch reg read offset=7000, value=c5000000
realy? nobody can help ?
I can help You with proper jboot images.
For problems with QCA please try repleace gsw section:
&gsw {
mediatek,port4 = "gmac";
mediatek,mt7530 = <1>;
};
But I'm not shure if it is enough. Is possible, that driver need rework. But first please try this.
I get router from @leks
The result of my work is in PR #1550
I don't know why work olny 3/5 GE ports. Maybe some AR8337 specialist could help.
Most likely because you did not pass the correct initvals
Exactly. But I have no idea what is wrong. Public datasheet didn't help me.
Most likely there is a debug tool in the stock firmware which lets you print out values of registers used by the driver.
I'm working on adding support for the EnGenius ESR600, which has an Atheros AR8327 (not AR8337) with MT7620A, and I'm having the same issue with two of the ports being non-functional. Ports 1,2, and 5 work... ports 3 and 4 do not. However -- booting with the stock U-Boot all the ports do work. I've used the U-Boot "mdio.r/mdio.w" commands to dump the AR8327 registers after U-Boot has initialized them for a tftpboot, and there are no differences that would explain this behavior. You can work from the datasheet register address to the mdio commands to read them with this trivial shell script:
#!/bin/sh
regaddr=$1
regaddr=$((regaddr >> 1))
r1=$((regaddr & 0x1E))
regaddr=$((regaddr >> 5))
r2=$((regaddr & 7))
regaddr=$((regaddr >> 3))
page=$((regaddr & 0x1FF))
printf 'mdio.w %d 0 %d\n' 0x18 $page
printf 'mdio.r %d %d\n' $((0x10 | r2)) $((r1 + 1))
printf 'mdio.r %d %d\n' $((0x10 | r2)) $r1
So the output given 0x80 (port1 status register) is:
mdio.w 24 0 0
mdio.r 18 1
mdio.r 18 0
Did anyone make any progress on figuring out the dead port issue??
hello i have patch where working all 5 port on lava lr25g001 and archer c5 v4 https://drive.google.com/file/d/14wF9qCgdTH9chfsr7ezU-u8Nas46Vl7X/view?usp=sharing
Thanks for that patch. At first reading it feels as though the code that's conditional on the mediatek,phy_init="disable" flag could be conditional on the "mediatek,mdio-mode". The engenius_esr600, lava_lr-25g001, and the edimax_ew-747x series are the only DTS files that use the mdio-mode=1 setting (I guess there may be other non-DTS based routers though).
+++ openwrt_lava/target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/gsw_mt7620.c 2018-11-29 21:21:10.349436742 +0300
@@ -88,6 +88,7 @@ static void mt7620_hw_init(struct mt7620
{
u32 i;
u32 val;
+ int init_phy4 = 1;
u32 is_BGA = (rt_sysc_r32(0x0c) >> 16) & 1;
rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
@@ -96,6 +97,11 @@ static void mt7620_hw_init(struct mt7620
/* Enable MIB stats */
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1), GSW_REG_MIB_CNT_EN);
+ if(!gsw->phy_init) {
+ init_phy4 = 0;
+ goto no_phy_init;
+ }
+
if (mdio_mode) {
u32 val;
@@ -184,6 +190,7 @@ static void mt7620_hw_init(struct mt7620
_mt7620_mii_write(gsw, 2, 16, 0x1515);
_mt7620_mii_write(gsw, 3, 16, 0x0f0f);
+no_phy_init:
/* CPU Port6 Force Link 1G, FC ON */
mtk_switch_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
@@ -191,6 +198,8 @@ static void mt7620_hw_init(struct mt7620
mtk_switch_w32(gsw, 0x7f7f7fe0, 0x0010);
/* setup port 4 */
+ if (!init_phy4)
+ return;
if (gsw->port4 == PORT4_EPHY) {
u32 val = rt_sysc_r32(SYSC_REG_CFG1);
@@ -245,6 +254,7 @@ static int mt7620_gsw_probe(struct platf
{
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
const char *port4 = NULL;
+ const char *phy_init = NULL;
struct mt7620_gsw *gsw;
struct device_node *np = pdev->dev.of_node;
@@ -257,6 +267,11 @@ static int mt7620_gsw_probe(struct platf
return PTR_ERR(gsw->base);
gsw->dev = &pdev->dev;
+ gsw->phy_init = 1;
+
+ of_property_read_string(np, "mediatek,phy_init", &phy_init);
+ if (phy_init && !strcmp(phy_init, "disable"))
+ gsw->phy_init = 0;
of_property_read_string(np, "mediatek,port4", &port4);
if (port4 && !strcmp(port4, "ephy"))
diff -ruNp openwrt/target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/gsw_mt7620.h openwrt_lava/target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/gsw_mt7620.h
--- openwrt/target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/gsw_mt7620.h 2018-11-29 20:18:16.601341759 +0300
+++ openwrt_lava/target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/gsw_mt7620.h 2018-11-29 21:21:10.349436742 +0300
@@ -102,6 +102,7 @@ struct mt7620_gsw {
void __iomem *base;
int irq;
int port4;
+ int phy_init;
unsigned long int autopoll;
};
Yeah, that's the piece I identified as being relevant to my ESR600. I haven't had a chance to try it out yet though. I may get to it tomorrow.
Looked over the existing code and what this patch does, and realized you could get almost the same effect by adding, in the DTS,
&gsw {
mediatek,port4="gmac";
};
which will skip the port4 init when the ethernet device also has mediatek,mdio-mode set.
The important difference between your patch and just doing the above is that you skip the setup of global page 0 and 2, so it doesn't execute
/* global page 0 */
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x8000);
_mt7620_mii_write(gsw, gsw->ephy_base + 0, 30, 0xa000);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 30, 0xa000);
_mt7620_mii_write(gsw, gsw->ephy_base + 2, 30, 0xa000);
_mt7620_mii_write(gsw, gsw->ephy_base + 3, 30, 0xa000);
_mt7620_mii_write(gsw, gsw->ephy_base + 0, 4, 0x05e1);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 4, 0x05e1);
_mt7620_mii_write(gsw, gsw->ephy_base + 2, 4, 0x05e1);
_mt7620_mii_write(gsw, gsw->ephy_base + 3, 4, 0x05e1);
/* global page 2 */
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0xa000);
_mt7620_mii_write(gsw, gsw->ephy_base + 0, 16, 0x1111);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 16, 0x1010);
_mt7620_mii_write(gsw, gsw->ephy_base + 2, 16, 0x1515);
_mt7620_mii_write(gsw, gsw->ephy_base + 3, 16, 0x0f0f);
so it would be interesting to know why those writes stop things from working. I tried moving them up into the tail of the preceding if/else so they're skipped if the ethernet is in mdio-mode, and that worked fine. But it leaves me wondering if we're just benefiting from not touching the PHYs after the stock U-Boot has set them up...
fixes and cleanup of MT7620 ethernet driver now in master, ready to backport after testing
it fixes the problem of some ports not working with AR8327 or other Atheros switches