Hello,
I have a SERCOMM NA502S (A1 Smart Home) hub. Since the A1 SmartHome service is discontinued, I want to repurpose the hub with OpenWRT.
Initially, I faced an issue where OpenWRT worked after installation, but I couldn’t access the device after a reboot (no ash over serial / no SSH). I tried various solutions from this forum without success.
Now, I have a new problem: after installing OpenWRT, I go to the webGUI LuCi -> System -> Backup / Flash Firmware -> Flash new firmware image. I upload the Sysupgrade file, but during the reboot, I get the following error message:
Uncompressing Kernel Image ... LZMA ERROR 1 - must RESET board to recover
I have tried the following Kernel files with their corresponding Sysupgrade files:
23.05.4
23.05.3
23.05.2
22.03.7 (The kernel installed, but when using the Sysupgrade file, I got an error message: “The device is supported, but the config is incompatible with the new image (1.1->1.0). Please upgrade without keeping config (sysupgrade -n). Image check failed.”)
I also tried the snapshot Kernel and Sysupgrade files.
i copied the whole loop down there
Any ideas what I am missing?
Please choose the operation:
1: Load system code to SDRAM via TFTP.
2: Load system code then write to Flash via TFTP.
3: Boot system code via Flash (default).
4: Entr boot command line interface.
9: Load Boot Loader code then write to Flash via TFTP.
STANDALONE_LOAD_ADDR is 0xa1200000
..
******************************************
Uboot StandAlone Entry
******************************************
0
******************************************
Uboot StandAlone Entry
******************************************
Flash Sector Number : 522.
***************************************************
Sercomm Boot Version 2.00.6
***************************************************
Entering Firmware : Everything is OK.
=================================================
Check image validation:
Image1 Header Magic Number --> OK
Image2 Header Magic Number --> OK
Image1 Header Checksum --> OK
Image2 Header Checksum --> OK
Image1 Data Checksum --> ........................................................................................OK
Image2 Data Checksum --> ...........................................OK
Image1: OK Image2: OK
=================================================
..kernel addr :0xbfd40000
flash base: 0xbfc00000, kernel addr :0xbfd40000, bootloader size: 0x80000, config size 0x80000, fac size : 0x40000
..Erasing NAND Flash...
.Writing to NAND Flash...
done
3: System Boot system code via Flash.
## Booting image at bfd40000 ...
Image Name: MIPS OpenWrt Linux-5.15.162
Image Type: MIPS Linux Kernel Image (lzma compressed)
Data Size: 5754115 Bytes = 5.5 MB
Load Address: 80001000
Entry Point: 80001000
........................................................................................ Verifying Checksum ... OK
Uncompressing Kernel Image ... LZMA ERROR 1 - must RESET board to recover
===================================================================
MT7621 stage1 code 13:15:05 (ASIC)
CPU=50000000 HZ BUS=16666666 HZ
==================================================================
Change MPLL source from XTAL to CR...
do MEMPLL setting..
MEMPLL Config : 0x11100000
3PLL mode + External loopback
=== XTAL-40Mhz === DDR-1200Mhz ===
PLL3 FB_DL: 0x9, 1/0 = 599/425 25000000
PLL2 FB_DL: 0x10, 1/0 = 647/377 41000000
PLL4 FB_DL: 0x14, 1/0 = 782/242 51000000
do DDR setting..[00320381]
Apply DDR3 Setting...(use customer AC)
0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120
--------------------------------------------------------------------------------
0000:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0001:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0002:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0003:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0004:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0005:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0006:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0007:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0008:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0009:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000E:| 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
000F:| 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0
0010:| 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
0011:| 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
0012:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0013:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0014:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0015:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0016:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0017:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0018:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0019:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
rank 0 coarse = 16
rank 0 fine = 40
B:| 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0
opt_dle value:11
DRAMC_R0DELDLY[018]=00001E1E
==================================================================
RX DQS perbit delay software calibration
==================================================================
1.0-15 bit dq delay value
==================================================================
bit| 0 1 2 3 4 5 6 7 8 9
--------------------------------------
0 | 13 7 11 10 13 6 13 5 5 12
10 | 8 13 8 13 6 11
--------------------------------------
==================================================================
2.dqs window
x=pass dqs delay value (min~max)center
y=0-7bit DQ of every group
input delay:DQS0 =30 DQS1 = 30
==================================================================
bit DQS0 bit DQS1
0 (1~58)29 8 (1~55)28
1 (1~52)26 9 (1~54)27
2 (1~55)28 10 (1~54)27
3 (1~56)28 11 (1~55)28
4 (1~59)30 12 (1~59)30
5 (1~55)28 13 (1~55)28
6 (1~58)29 14 (1~56)28
7 (1~58)29 15 (1~57)29
==================================================================
3.dq delay value last
==================================================================
bit| 0 1 2 3 4 5 6 7 8 9
--------------------------------------
0 | 14 11 13 12 13 8 14 6 7 15
10 | 11 15 8 15 8 12
==================================================================
==================================================================
TX perbyte calibration
==================================================================
DQS loop = 15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqsdly_pass[0]=15, finish count=1
dqs_perbyte_dly.last_dqsdly_pass[1]=15, finish count=2
DQ loop=15, cmp_err_1 = ffff01aa
DQ loop=14, cmp_err_1 = ffff0080
dqs_perbyte_dly.last_dqdly_pass[1]=14, finish count=1
DQ loop=13, cmp_err_1 = ffff0080
DQ loop=12, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqdly_pass[0]=12, finish count=2
byte:0, (DQS,DQ)=(9,8)
byte:1, (DQS,DQ)=(8,8)
20,data:89
[EMI] DRAMC calibration passed
===================================================================
MT7621 stage1 code done
CPU=50000000 HZ BUS=16666666 HZ
===================================================================
U-Boot 1.1.3 (May 2 2017 - 17:01:08)
Board: Ralink APSoC DRAM: 256 MB
relocate_code Pointer at: 8ffac000
Config XHCI 40M PLL
******************************
Software System Reset Occurred
******************************
Allocate 16 byte aligned buffer: 8ffe1130
Enable NFI Clock
# MTK NAND # : Use HW ECC
NAND ID [C8 D1 80 95 40]
Device not found, ID: c8d1
Not Support this Device!
chip_mode=00000001
Support this Device in MTK table! c8d1
select_chip
[NAND]select ecc bit:4, sparesize :64 spare_per_sector=16
Signature matched and data read!
load_fact_bbt success 1023
load fact bbt success
[mtk_nand] probe successfully!
mtd->writesize=2048 mtd->oobsize=64, mtd->erasesize=131072 devinfo.iowidth=8
Env addr : 0x80000
..============================================
Ralink UBoot Version: 4.2.1.0
--------------------------------------------
ASIC MT7621AS (MAC to MT7530 Mode)
DRAM_CONF_FROM: Auto-Detection
DRAM_TYPE: DDR3
DRAM bus: 16 bit
Xtal Mode=3 OCP Ratio=1/3
Flash component: NAND Flash
Date:May 2 2017 Time:17:01:08
============================================
icache: sets:256, ways:4, linesz:32 ,total:32768
dcache: sets:256, ways:4, linesz:32 ,total:32768
##### The CPU freq = 880 MHZ ####
estimate memory size =256 Mbytes
Reset switch ...
#Reset_MT7530
Please choose the operation:
1: Load system code to SDRAM via TFTP.
2: Load system code then write to Flash via TFTP.
3: Boot system code via Flash (default).
4: Entr boot command line interface.
9: Load Boot Loader code then write to Flash via TFTP.
STANDALONE_LOAD_ADDR is 0xa1200000
..
******************************************
Uboot StandAlone Entry
******************************************
******************************************
Uboot StandAlone Entry
******************************************