IPQ5018, YT9215s, and 1000Base-X / 2500Base-X

For Developers
21

No major issue. One nitpick that setting mtu somehow requires resetting the interface:

root@OpenWrt:~# ifconfig eth0 mtu 1502
[  511.608502] ipq5018-gmac-dwmac 39c00000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-0
[  511.609782] ipq5018-gmac-dwmac 39c00000.ethernet eth0: Link is Down
[  511.691014] ipq5018-gmac-dwmac 39c00000.ethernet eth0: PHY [88000.mdio-1:07] driver [Qualcomm Atheros IPQ5018 internal PHY] (irq=POLL)
[  511.691123] ipq5018-gmac-dwmac 39c00000.ethernet eth0: No Safety Features support found
[  511.702150] ipq5018-gmac-dwmac 39c00000.ethernet eth0: IEEE 1588-2008 Advanced Timestamp supported
[  511.709938] ipq5018-gmac-dwmac 39c00000.ethernet eth0: configuring for phy/sgmii link mode
root@OpenWrt:~# [  512.412276] br-eth0sw: port 1(cpu) entered disabled state
[  512.413345] yt921x 90000.mdio-1:1d cpu: Link is Down
[  514.496821] yt921x 90000.mdio-1:1d cpu: Link is Up - 1Gbps/Full - flow control rx/tx
[  514.496901] br-eth0sw: port 1(cpu) entered blocking state
[  514.503700] br-eth0sw: port 1(cpu) entered forwarding state
[  514.811031] ipq5018-gmac-dwmac 39c00000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
22

I was just reviewing how the wan port is wired up:

xiaomi,cr8818)
		ucidef_set_interface "eth0sw" device "cpu wan" protocol none ipv6 0
		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" "eth0"

and

port@4 {
				reg = <4>;
				label = "cpu";
				phy-mode = "internal";
				phy-handle = <&sw_phy4>;
			};

			port@8 {
				reg = <8>;
				phy-mode = "2500base-x";
				ethernet = <&dp2>;

				fixed-link {
					speed = <2500>;
					full-duplex;
					pause;
					asym-pause;
				};
			};

If I understand correctly, port4 (cpu) is wired to the gmac0 (dp1) / ipq5018 internal GE PHY.
If the switch driver supports multiple CPU ports, why don't you just add ethernet = <&dp1>; ?

23

If the switch driver supports multiple CPU ports

No.