theMan, thanks for responding. This is very inspiring to hear that you have the same router and have succeeded in what I am trying to do
.
I don't have a backup of the ART partition specifically, all I have is a BIN file which is the whole binary contents of the original 16MB chip with stock firmware. I can open it and locate the blocks which contain the MAC address, but I don't know how to separate it into individual partitions.
Can I ask what chip you upgraded to and how you got that bootloader with GUI? I already modified mine to get serial I/O so I can see everything that is going on with the bootloader and firmware. This is how I did it:

A 4-way female DuPont connector with long wire tails is connected to header J1 on the PCB. These are actually the Power and Reset button wires cut from an old PC case and connectors superglued together side-by-side. The long wires ensure the PCB can still be released from the casing to be worked on in future without the need to de-solder the connections from J1.

Small piece of plastic removed from the perimeter lip of the case's base, and connector superglued down to the plastic with the test points facing upwards.

Pin holes look pretty neat from the outside and will be hidden from view when the router is placed on its vertical stand anyway.

A label outlining the functions of the pins, and the order of the pins is affixed below, to avoid any mishaps.

Individual male DuPont pin connectors (or preferably a single quad pin one) can easily be inserted.
This was the last boot log I captured from it with the original chip in it, before changing to the 32MB one. Maybe I should capture another log now that the chip has been swapped out.
===================================================================
MT7621 stage1 code 13:14:00 (ASIC)
CPU=50000000 HZ BUS=16666666 HZ
==================================================================
Change MPLL source from XTAL to CR...
do MEMPLL setting..
MEMPLL Config : 0x11100000
3PLL mode + External loopback
=== XTAL-40Mhz === DDR-1200Mhz ===
PLL3 FB_DL: 0xe, 1/0 = 667/357 39000000
PLL4 FB_DL: 0x11, 1/0 = 540/484 45000000
PLL2 FB_DL: 0x14, 1/0 = 723/301 51000000
do DDR setting..\[00320000\]
Apply DDR3 Setting...(use customer AC)
0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120
0000:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0001:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0002:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0003:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0004:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0005:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0006:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0007:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0008:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0009:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000E:| 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
000F:| 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0
0010:| 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
0011:| 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
0012:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0013:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0014:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0015:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0016:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0017:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0018:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0019:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
rank 0 coarse = 15
rank 0 fine = 80
B:| 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0
opt_dle value:9
DRAMC_R0DELDLY\[018\]=00001E1F
==================================================================
RX DQS perbit delay software calibration
==================================================================
1.0-15 bit dq delay value
==================================================================
bit| 0 1 2 3 4 5 6 7 8 9
---
0 | 15 9 15 14 15 11 15 9 6 13
10 | 9 15 9 14 8 14
---
==================================================================
2.dqs window
x=pass dqs delay value (min\~max)center
y=0-7bit DQ of every group
input delay:DQS0 =31 DQS1 = 30
==================================================================
bit DQS0 bit DQS1
0 (0\~58)29 8 (1\~56)28
1 (0\~56)28 9 (1\~56)28
2 (0\~58)29 10 (1\~57)29
3 (1\~60)30 11 (1\~55)28
4 (0\~61)30 12 (1\~58)29
5 (1\~61)31 13 (1\~56)28
6 (0\~59)29 14 (1\~58)29
7 (1\~62)31 15 (1\~59)30
==================================================================
3.dq delay value last
==================================================================
bit| 0 1 2 3 4 5 6 7 8 9
---
0 | 15 12 15 15 15 11 15 9 8 15
10 | 10 15 10 15 9 14
==================================================================
==================================================================
TX perbyte calibration
==================================================================
DQS loop = 15, cmp_err_1 = ffff2a15
DQS loop = 14, cmp_err_1 = ffff0801
DQS loop = 13, cmp_err_1 = ffff0001
dqs_perbyte_dly.last_dqsdly_pass\[1\]=13, finish count=1
DQS loop = 12, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqsdly_pass\[0\]=12, finish count=2
DQ loop=15, cmp_err_1 = ffff00aa
dqs_perbyte_dly.last_dqdly_pass\[1\]=15, finish count=1
DQ loop=14, cmp_err_1 = ffff0082
DQ loop=13, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqdly_pass\[0\]=13, finish count=2
byte:0, (DQS,DQ)=(8,8)
byte:1, (DQS,DQ)=(8,9)
20,data:88
\[EMI\] DRAMC calibration passed
===================================================================
MT7621 stage1 code done
CPU=50000000 HZ BUS=16666666 HZ
===================================================================
U-Boot 1.1.3 (Nov 17 2014 - 08:29:53)
Board: Ralink APSoC DRAM: 128 MB
relocate_code Pointer at: 87fb4000
Config XHCI 40M PLL
flash manufacture id: c2, device id 20 18
find flash: MX25L12805D
\*\*\* Warning - bad CRC, using default environment
## ============================================
Ralink UBoot Version: 4.2.1.0
# ASIC MT7621AS (MAC to MT7530 Mode)
DRAM_CONF_FROM: Auto-Detection
DRAM_TYPE: DDR3
DRAM bus: 16 bit
Xtal Mode=3 OCP Ratio=1/3
Flash component: SPI Flash
Date:Nov 17 2014 Time:08:29:53
icache: sets:256, ways:4, linesz:32 ,total:32768
dcache: sets:256, ways:4, linesz:32 ,total:32768
##### The CPU freq = 880 MHZ
estimate memory size =128 Mbytes
Reset switch ...
#Reset_MT7530
set LAN/WAN LLLLW
Example expects ABI version 2
Actual U-Boot ABI version 2
e\[31m\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*
Uboot StandAlone Entry
\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*e\[0m
0, cmd
1, 0x0000000D
cmd : 0x0000000D
Press Ctrl+C to Enter the Main loop...
Example expects ABI version 2
Actual U-Boot ABI version 2
e\[31m\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*
Uboot StandAlone Entry
\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*e\[0m
0, cmd
1, 0x0000000F
cmd : 0x0000000F
Enter NMRP_main
Flash Sector Number : 256.
NetTxPacket = 0x87FE4300
KSEG1ADDR(NetTxPacket) = 0xA7FE4300
NetLoop,call eth_halt !
NetLoop,call eth_init !
Trying Eth0 (10/100-M)
Waitting for RX_DMA_BUSY status Start... done
ETH_STATE_ACTIVE!!
NMRP_FLASH_SIZE_buffer --> a1000000.
NMRP:LISTENING
### No NMRP Server found
Example expects ABI version 2
Actual U-Boot ABI version 2
e\[31m\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*
Uboot StandAlone Entry
\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*e\[0m
0, boot
Flash Sector Number : 256.
---
Sercomm Boot Version 1.13.0
---
Entering Firmware : Everything is OK.
flash base: 0xbfc00000, kernel addr :0xbfc50000, bootloader size: 0x30000, config size 0x10000, fac size : 0x10000
kernel addr :0xbfc50000