Help Needed: Porting DTS from Kernel 4.4 to Kernel 5.5 - Wireless Driver Issue

Hello OpenWrt Community,

I am currently working on porting the DTS file of a router from kernel 4.4 to kernel 5.5. While most of the functionalities are working fine, I am facing issues with the wireless driver not initializing correctly.
Below are the relevant logs:

[    9.971450] kmodloader: loading kernel modules from /etc/modules.d/*
[   10.161278] Loading modules backported from Linux version v6.1.24-0-g0102425ac76b
[   10.168942] Backport generated by backports.git v5.15.92-1-44-gd6ea70fafd36
[   10.240520] pci 0000:00:00.0: enabling device (0006 -> 0007)
[   10.246236] mt7915e_hif 0000:01:00.0: enabling device (0000 -> 0002)
[   10.253073] pci 0000:00:01.0: enabling device (0006 -> 0007)
[   10.258809] mt7915e 0000:02:00.0: enabling device (0000 -> 0002)
[   10.429199] mt7915e 0000:02:00.0: HW/SW Version: 0x8a108a10, Build Time: 20220929104113a
[   10.429199] 
[   10.455614] mt7915e 0000:02:00.0: WM Firmware Version: ____000000, Build Time: 20220929104145
[   10.493699] mt7915e 0000:02:00.0: WA Firmware Version: DEV_000000, Build Time: 20220929104205
[   10.614145] mt7915e 0000:02:00.0: eeprom load fail, use default bin
[   10.620603] mt7915e 0000:02:00.0: Direct firmware load for mediatek/mt7915_eeprom_dbdc.bin failed with error -2
[   10.630704] mt7915e 0000:02:00.0: Falling back to sysfs fallback for: mediatek/mt7915_eeprom_dbdc.bin

t seems like the driver is unable to load the EEPROM and firmware properly. I have double-checked the firmware file locations and everything seems to be in place.

Has anyone encountered similar issues or can provide guidance on how to resolve this?

Below are the DTS files for both kernel versions:

DTS for Kernel 4.4:

/dts-v1/;

/ {
	model = "MediaTek MT7621 RFB (802.11ax,SNOR)";
	#size-cells = <0x01>;
	#address-cells = <0x01>;
	compatible = "mediatek,mt7621-rfb-nor\0mediatek,mt7621-soc";

	sysbusclock@0 {
		#clock-cells = <0x00>;
		phandle = <0x07>;
		linux,phandle = <0x07>;
		compatible = "mtk,mt7621-sys-bus-clock";
	};

	sdhci@1e130000 {
		pinctrl-0 = <0x0d>;
		interrupts = <0x00 0x14 0x04>;
		reg = <0x1e130000 0x4000>;
		status = "okay";
		interrupt-parent = <0x01>;
		pinctrl-names = "default";
		compatible = "mediatek,mt7621-sdhci";
	};

	gsw {
		interrupts = <0x00 0x17 0x04>;
		mediatek,mdio = <0x0c>;
		mediatek,mcm;
		resets = <0x03 0x02>;
		#size-cells = <0x00>;
		interrupt-parent = <0x01>;
		#address-cells = <0x01>;
		compatible = "mediatek,mt753x";
		reset-names = "mcm";
		mediatek,portmap = "llllw";
		mt7530,direct-phy-access;

		port@6 {
			reg = <0x06>;
			phy-mode = "trgmii";
			compatible = "mediatek,mt753x-port";

			fixed-link {
				full-duplex;
				speed = <0x3e8>;
			};
		};

		mdio-bus {
			#size-cells = <0x00>;
			#address-cells = <0x01>;
		};

		port@5 {
			reg = <0x05>;
			phy-mode = "rgmii";
			compatible = "mediatek,mt753x-port";

			fixed-link {
				full-duplex;
				speed = <0x3e8>;
			};
		};
	};

	cpuintc@0 {
		#interrupt-cells = <0x01>;
		interrupt-controller;
		#address-cells = <0x00>;
		compatible = "mti,cpu-interrupt-controller";
	};

	palmbus@1e000000 {
		ranges = <0x00 0x1e000000 0xfffff>;
		reg = <0x1e000000 0x100000>;
		#size-cells = <0x01>;
		#address-cells = <0x01>;
		compatible = "palmbus";

		spi@b00 {
			pinctrl-0 = <0x08>;
			reg = <0xb00 0x100>;
			clocks = <0x07>;
			resets = <0x03 0x12>;
			#size-cells = <0x00>;
			status = "okay";
			pinctrl-names = "default";
			#address-cells = <0x01>;
			compatible = "mediatek,mt7621-spi";
			reset-names = "spi";

			m25p80@0 {
				reg = <0x00>;
				#size-cells = <0x01>;
				#address-cells = <0x01>;
				m25p,chunked-io = <0x20>;
				compatible = "jedec,spi-nor";
				spi-max-frequency = <0x989680>;

				partition@90000 {
					reg = <0x90000 0xf70000>;
					label = "firmware";
				};

				partition@0 {
					reg = <0x00 0x30000>;
					label = "Bootloader";
				};

				partition@50000 {
					reg = <0x50000 0x40000>;
					label = "Factory";
				};

				partition@30000 {
					reg = <0x30000 0x10000>;
					label = "Config";
				};
			};
		};

		uartlite@c00 {
			reg-io-width = <0x04>;
			reg-shift = <0x02>;
			interrupts = <0x00 0x1a 0x04>;
			reg = <0xc00 0x100>;
			clocks = <0x02>;
			interrupt-parent = <0x01>;
			no-loopback-test;
			compatible = "mediatek,mt6577-uart\0ns16550a";
			clock-frequency = <0x2faf080>;
		};

		nand@3000 {
			pinctrl-0 = <0x0a>;
			reg = <0x3000 0x800>;
			ecc-engine = <0x09>;
			#size-cells = <0x01>;
			status = "disabled";
			pinctrl-names = "default";
			#address-cells = <0x01>;
			compatible = "mediatek,mt7621-nfc";
		};

		uartfull@e00 {
			reg-io-width = <0x04>;
			reg-shift = <0x02>;
			interrupts = <0x00 0x1c 0x04>;
			reg = <0xe00 0x100>;
			clocks = <0x02>;
			status = "okay";
			interrupt-parent = <0x01>;
			no-loopback-test;
			compatible = "mediatek,mt6577-uart\0ns16550a";
			clock-frequency = <0x2faf080>;
		};

		i2c@900 {
			pinctrl-0 = <0x04>;
			reg = <0x900 0x100>;
			clocks = <0x02>;
			resets = <0x03 0x10>;
			#size-cells = <0x00>;
			status = "disabled";
			pinctrl-names = "default";
			#address-cells = <0x01>;
			compatible = "mediatek,mt7621-i2c";
			reset-names = "i2c";
		};

		gdma@2800 {
			phandle = <0x06>;
			#dma-channels = <0x10>;
			interrupts = <0x00 0x0d 0x04>;
			reg = <0x2800 0x800>;
			resets = <0x03 0x0e>;
			#dma-cells = <0x01>;
			status = "disabled";
			interrupt-parent = <0x01>;
			linux,phandle = <0x06>;
			compatible = "mtk,rt3883-gdma";
			reset-names = "dma";
			#dma-requests = <0x10>;
		};

		gpio@600 {
			interrupts = <0x00 0x0c 0x04>;
			reg = <0x600 0x100>;
			#size-cells = <0x00>;
			interrupt-parent = <0x01>;
			#address-cells = <0x01>;
			compatible = "mtk,mt7621-gpio";

			bank@0 {
				#gpio-cells = <0x02>;
				phandle = <0x10>;
				reg = <0x00>;
				gpio-controller;
				linux,phandle = <0x10>;
				compatible = "mtk,mt7621-gpio-bank";
			};

			bank@1 {
				#gpio-cells = <0x02>;
				reg = <0x01>;
				gpio-controller;
				compatible = "mtk,mt7621-gpio-bank";
			};

			bank@2 {
				#gpio-cells = <0x02>;
				reg = <0x02>;
				gpio-controller;
				compatible = "mtk,mt7621-gpio-bank";
			};
		};

		sysc@0 {
			reg = <0x00 0x100>;
			compatible = "mtk,mt7621-sysc";
		};

		i2s@a00 {
			txdma-req = <0x02>;
			dmas = <0x06 0x04 0x06 0x06>;
			interrupts = <0x00 0x10 0x04>;
			reg = <0xa00 0x100>;
			clocks = <0x05>;
			rxdma-req = <0x03>;
			resets = <0x03 0x11>;
			status = "disabled";
			interrupt-parent = <0x01>;
			compatible = "mediatek,mt7621-i2s";
			reset-names = "i2s";
			dma-names = "tx\0rx";
		};

		hsdma@7000 {
			#dma-channels = <0x01>;
			interrupts = <0x00 0x0b 0x04>;
			reg = <0x7000 0x1000>;
			resets = <0x03 0x05>;
			#dma-cells = <0x01>;
			status = "disabled";
			interrupt-parent = <0x01>;
			compatible = "mediatek,mt7621-hsdma";
			reset-names = "hsdma";
			#dma-requests = <0x01>;
		};

		ecc@3800 {
			phandle = <0x09>;
			reg = <0x3800 0x800>;
			status = "disabled";
			linux,phandle = <0x09>;
			compatible = "mediatek,mt7621-ecc";
		};

		memc@5000 {
			reg = <0x5000 0x1000>;
			compatible = "mtk,mt7621-memc";
		};

		wdt@100 {
			reg = <0x100 0x100>;
			compatible = "mtk,mt7621-wdt";
		};

		uartfull@d00 {
			reg-io-width = <0x04>;
			reg-shift = <0x02>;
			interrupts = <0x00 0x1b 0x04>;
			reg = <0xd00 0x100>;
			clocks = <0x02>;
			status = "okay";
			interrupt-parent = <0x01>;
			no-loopback-test;
			compatible = "mediatek,mt6577-uart\0ns16550a";
			clock-frequency = <0x2faf080>;
		};
	};

	usb-phy@1e1d0000 {
		ranges;
		reg = <0x1e1d0000 0x300>;
		#size-cells = <0x01>;
		status = "okay";
		#address-cells = <0x01>;
		compatible = "mediatek,mt7621-u3phy\0mediatek,mt2701-u3phy";

		usb-phy@0x1e1d0900 {
			phandle = <0x13>;
			#phy-cells = <0x01>;
			clock-names = "ref";
			reg = <0x1e1d0900 0x700>;
			clocks = <0x11>;
			linux,phandle = <0x13>;
		};

		usb-phy@0x1e1d0800 {
			phandle = <0x12>;
			#phy-cells = <0x01>;
			clock-names = "ref";
			reg = <0x1e1d0800 0x100>;
			clocks = <0x11>;
			linux,phandle = <0x12>;
		};

		usb-phy@0x1e1d1000 {
			phandle = <0x14>;
			#phy-cells = <0x01>;
			clock-names = "ref";
			reg = <0x1e1d1000 0x100>;
			clocks = <0x11>;
			linux,phandle = <0x14>;
		};
	};

	pinctrl {
		pinctrl-0 = <0x16>;
		pinctrl-names = "default";
		compatible = "mtk,mtkmips-pinmux";

		pinctrl0 {
			phandle = <0x16>;
			linux,phandle = <0x16>;

			gpio {
				mtk,function = "gpio";
				mtk,group = "i2c";
			};

			uart3 {
				mtk,function = "uart3";
				mtk,group = "uart3";
			};

			uart2 {
				mtk,function = "uart2";
				mtk,group = "uart2";
			};
		};

		rgmii2 {

			rgmii2 {
				mtk,function = "rgmii2";
				mtk,group = "rgmii2";
			};
		};

		sdhci {
			phandle = <0x0d>;
			linux,phandle = <0x0d>;

			sdhci {
				mtk,function = "sdhci";
				mtk,group = "sdhci";
			};
		};

		rgmii1 {

			rgmii1 {
				mtk,function = "rgmii1";
				mtk,group = "rgmii1";
			};
		};

		mdio {

			mdio {
				mtk,function = "mdio";
				mtk,group = "mdio";
			};
		};

		i2c {
			phandle = <0x04>;
			linux,phandle = <0x04>;

			i2c {
				mtk,function = "i2c";
				mtk,group = "i2c";
			};
		};

		pcie {
			phandle = <0x0e>;
			linux,phandle = <0x0e>;

			pcie {
				mtk,function = "gpio";
				mtk,group = "pcie";
			};
		};

		uart3 {

			uart3 {
				mtk,function = "uart3";
				mtk,group = "uart3";
			};
		};

		uart1 {

			uart1 {
				mtk,function = "uart1";
				mtk,group = "uart1";
			};
		};

		nand {
			phandle = <0x0a>;
			linux,phandle = <0x0a>;

			sdhci-nand {
				mtk,function = "nand2";
				mtk,group = "sdhci";
			};

			spi-nand {
				mtk,function = "nand1";
				mtk,group = "spi";
			};
		};

		spi {
			phandle = <0x08>;
			linux,phandle = <0x08>;

			spi {
				mtk,function = "spi";
				mtk,group = "spi";
			};
		};

		uart2 {

			uart2 {
				mtk,function = "uart2";
				mtk,group = "uart2";
			};
		};
	};

	cpuclock@0 {
		#clock-cells = <0x00>;
		phandle = <0x15>;
		linux,phandle = <0x15>;
		compatible = "mtk,mt7621-cpu-clock";
	};

	rstctrl {
		phandle = <0x03>;
		linux,phandle = <0x03>;
		compatible = "ralink,rt2880-reset";
		#reset-cells = <0x01>;
	};

	apll@0 {
		#clock-cells = <0x00>;
		phandle = <0x05>;
		linux,phandle = <0x05>;
		compatible = "fixed-clock";
		clock-frequency = <0x1017df80>;
	};

	raeth@1e100000 {
		interrupts = <0x00 0x03 0x04>;
		reg = <0x1e100000 0xe000>;
		status = "disabled";
		interrupt-parent = <0x01>;
		compatible = "mediatek,mt7621-eth";
		mediatek,ethsys = <0x0b>;
	};

	gpio-keys-polled {
		poll-interval = <0x14>;
		#size-cells = <0x00>;
		#address-cells = <0x01>;
		compatible = "gpio-keys-polled";

		reset {
			gpios = <0x10 0x12 0x01>;
			linux,code = <0x198>;
			label = "reset";
		};
	};

	aliases {
		serial0 = "/palmbus@1e000000/uartlite@c00";
	};

	interrupt-controller@1fbc0000 {
		#interrupt-cells = <0x03>;
		interrupt-controller;
		phandle = <0x01>;
		reg = <0x1fbc0000 0x2000>;
		linux,phandle = <0x01>;
		compatible = "mti,gic";
		mti,reserved-cpu-vectors = <0x07>;

		timer {
			interrupts = <0x01 0x01 0x00>;
			clocks = <0x15>;
			compatible = "mti,gic-timer";
		};
	};

	sysclock125M@0 {
		#clock-cells = <0x00>;
		phandle = <0x11>;
		linux,phandle = <0x11>;
		compatible = "fixed-clock";
		clock-frequency = <0x7735940>;
	};

	clkctrl {
		#clock-cells = <0x01>;
		phandle = <0x0f>;
		linux,phandle = <0x0f>;
		compatible = "ralink,rt2880-clock";
	};

	cpus {

		cpu@0 {
			compatible = "mips,mips1004Kc";
		};

		cpu@1 {
			compatible = "mips,mips1004Kc";
		};
	};

	sysclock50M@0 {
		#clock-cells = <0x00>;
		phandle = <0x02>;
		linux,phandle = <0x02>;
		compatible = "fixed-clock";
		clock-frequency = <0x2faf080>;
	};

	pcie@1e140000 {
		pinctrl-0 = <0x0e>;
		ranges = <0x2000000 0x00 0x00 0x60000000 0x00 0x10000000 0x1000000 0x00 0x00 0x1e160000 0x00 0x10000>;
		interrupts = <0x00 0x04 0x04 0x00 0x18 0x04 0x00 0x19 0x04>;
		clock-names = "pcie0\0pcie1\0pcie2";
		reg = <0x1e140000 0x40000>;
		clocks = <0x0f 0x18 0x0f 0x19 0x0f 0x1a>;
		bus-range = <0x00 0xff>;
		reset-gpios = <0x10 0x13 0x01>;
		resets = <0x03 0x18 0x03 0x19 0x03 0x1a>;
		reset-gpio-names = "pcie";
		#size-cells = <0x02>;
		status = "okay";
		interrupt-parent = <0x01>;
		device_type = "pci";
		pinctrl-names = "default";
		#address-cells = <0x03>;
		compatible = "mediatek,mt7621-pci";
		reset-names = "pcie0\0pcie1\0pcie2";

		pcie1 {
			reg = <0x800 0x00 0x00 0x00 0x00>;
			#size-cells = <0x02>;
			device_type = "pci";
			#address-cells = <0x03>;
		};

		pcie0 {
			reg = <0x00 0x00 0x00 0x00 0x00>;
			#size-cells = <0x02>;
			device_type = "pci";
			#address-cells = <0x03>;
		};

		pcie2 {
			reg = <0x1000 0x00 0x00 0x00 0x00>;
			#size-cells = <0x02>;
			device_type = "pci";
			#address-cells = <0x03>;
		};
	};

	ethsys@1e000000 {
		phandle = <0x0b>;
		reg = <0x1e000000 0x8000>;
		linux,phandle = <0x0b>;
		compatible = "mediatek,mt7621-ethsys\0syscon";
	};

	usb@1e1c0000 {
		reg-names = "mac\0ippc";
		interrupts = <0x00 0x16 0x04>;
		clock-names = "sys_ck\0free_ck\0ahb_ck\0dma_ck";
		reg = <0x1e1c0000 0x1000 0x1e1d0700 0x100>;
		clocks = <0x11 0x11 0x11 0x11>;
		status = "okay";
		interrupt-parent = <0x01>;
		compatible = "mediatek,mt7621-xhci\0mediatek,mt2701-xhci";
		phys = <0x12 0x03 0x13 0x04 0x14 0x03>;
	};

	hnat@1e100000 {
		mtketh-wan = "eth1";
		mtketh-ppd = "eth0";
		reg = <0x1e100000 0x3000>;
		resets = <0x0b 0x00>;
		mtketh-max-gmac = <0x02>;
		status = "okay";
		ext-devices = "rax0\0ra0\0rax1\0ra1\0rax2\0ra2\0rax3\0ra3\0apclix0\0apcli0";
		compatible = "mediatek,mtk-hnat_v1";
		reset-names = "mtketh";
	};

	chosen {
		bootargs = "console=ttyS0,115200";
	};

	crypto@1e004000 {
		interrupts = <0x00 0x13 0x04>;
		reg = <0x1e004000 0x1000>;
		status = "okay";
		interrupt-parent = <0x01>;
		compatible = "mediatek,mtk-eip93";
	};

	ethernet@1e100000 {
		interrupts = <0x00 0x03 0x04>;
		reg = <0x1e100000 0xe000>;
		#size-cells = <0x00>;
		status = "okay";
		interrupt-parent = <0x01>;
		#address-cells = <0x01>;
		compatible = "mediatek,mt7621-eth\0syscon";
		mediatek,ethsys = <0x0b>;

		mdio-bus {
			phandle = <0x0c>;
			#size-cells = <0x00>;
			#address-cells = <0x01>;
			linux,phandle = <0x0c>;

			ethernet-phy@1f {
				reg = <0x1f>;
				phy-mode = "rgmii";
			};
		};

		mac@1 {
			reg = <0x01>;
			phy-mode = "rgmii";
			compatible = "mediatek,eth-mac";

			fixed-link {
				full-duplex;
				speed = <0x3e8>;
				pause;
			};
		};

		mac@0 {
			reg = <0x00>;
			phy-mode = "trgmii";
			compatible = "mediatek,eth-mac";

			fixed-link {
				full-duplex;
				speed = <0x3e8>;
				pause;
			};
		};
	};
};

DTS for Kernel 5.5:

#include "mt7621.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

/ {
    compatible = "invendis,silbo-RS6X", "mediatek,mt7621-soc";
    model = "Invendis Silbo-RS6X";

    chosen {
        bootargs = "console=ttyS0,115200";
    };

    keys {
        compatible = "gpio-keys";

        reset {
            label = "reset";
            gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
            linux,code = <KEY_RESTART>;
        };
    };
};

&sdhci {
    status = "okay";
};

&spi0 {
    status = "okay";

    flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0>;
        spi-max-frequency = <10000000>;
        broken-flash-reset;

        partitions {
            compatible = "fixed-partitions";
            #address-cells = <1>;
            #size-cells = <1>;

            partition@0 {
                label = "Bootloader";
                reg = <0x00000000 0x30000>;
            };

            partition@30000 {
                label = "Config";
                reg = <0x30000 0x10000>;
            };

            factory: partition@40000 {
                label = "Factory";
                reg = <0x40000 0x80000>;

            };

	    partition@c0000 {  // Start address adjusted to 0xc0000 (0x40000 + 0x80000)
            	label = "firmware";
        	reg = <0x0c0000 0x1f40000>;  // Updated size (original size - 0x40000)
    	    };

        };
    };
};

&ethernet {
    mtd-mac-address = <&factory 0xe000>;
};

&pcie {
    status = "okay";
};

&pcie1 {
    wifi@0,0 {
        compatible = "mediatek,mt76";
        reg = <0x0000 0 0 0 0>;
        mediatek,mtd-eeprom = <&factory 0x0>;
    };
};


&gmac0 {
    mtd-mac-address = <&factory 0xe000>;
};

&switch0 {
    ports {
        port@0 {
            status = "okay";
            label = "eth0.1";
            mtd-mac-address = <&factory 0xe000>;
            mtd-mac-address-increment = <1>;
        };

        port@1 {
            status = "okay";
            label = "eth0.2";
            mtd-mac-address = <&factory 0xe000>;
            mtd-mac-address-increment = <2>;
        };

        port@2 {
            status = "okay";
            label = "eth0.3";
            mtd-mac-address = <&factory 0xe000>;
            mtd-mac-address-increment = <3>;
        };

    };
};

&state_default {
    gpio {
        groups = "wdt", "uart2";
        function = "gpio";
    };
};

&uartlite2 {
    status = "okay";
};

&xhci {
    status = "okay";
};

&i2c {
    status = "okay";
    compatible = "mediatek,mt7621-i2c";

    i2c-gpio,delay-us = <10>;

    pca9535@23 {
        compatible = "nxp,pca9535";
        reg = <0x23>;
        gpio-controller;
    };

    pca9535@22 {
        compatible = "nxp,pca9535";
        reg = <0x22>;
        gpio-controller;
    };

    pt7c4337: rtc@68 {
        status = "okay";
        compatible = "pericom,pti4337";
        reg = <0x68>;
        gpio-controller;
    };
};

DTS for Similar Device on Kernel 5.5 which has openwrt support(1):

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT

#include "mt7621.dtsi"

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>

/ {
	compatible = "belkin,rt1800", "mediatek,mt7621-soc";
	model = "Belkin RT1800";

	aliases {
		led-boot = &led_power;
		led-failsafe = &led_power;
		led-running = &led_power;
		led-upgrade = &led_power;
	};

	chosen {
		bootargs = "console=ttyS0,115200";
	};

	keys {
		compatible = "gpio-keys";

		reset {
			label = "reset";
			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_RESTART>;
		};

		wps {
			label = "wps";
			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_WPS_BUTTON>;
		};
	};

	leds {
		compatible = "gpio-leds";

		led-wps {
			color = <LED_COLOR_ID_AMBER>;
			function = LED_FUNCTION_WPS;
			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
		};

		led_power: led-power {
			label = "white:power";
			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
			default-state = "on";
		};

		led-wan2 {
			color = <LED_COLOR_ID_AMBER>;
			function = LED_FUNCTION_WAN;
			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
		};

		led-wan {
			color = <LED_COLOR_ID_WHITE>;
			function = LED_FUNCTION_WAN;
			gpios = <&switch0 0 GPIO_ACTIVE_LOW>;
		};
	};
};

&nand {
	status = "okay";

	partitions {
		compatible = "fixed-partitions";
		#address-cells = <1>;
		#size-cells = <1>;

		partition@0 {
			label = "Boot";
			reg = <0x0 0x80000>;
			read-only;
		};

		partition@80000 {
			label = "Config";
			reg = <0x80000 0x80000>;
		};

		factory: partition@100000 {
			label = "Factory";
			reg = <0x100000 0x80000>;
			read-only;
		};

		partition@180000 {
			label = "firmware";
			reg = <0x180000 0x3000000>;

			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "kernel";
				reg = <0x0 0x400000>;
			};

			partition@400000 {
				label = "ubi";
				reg = <0x400000 0x2c00000>;
			};
		};

		partition@3180000 {
			label = "alt_firmware";
			reg = <0x3180000 0x3000000>;
			read-only;
		};

		partition@6180000 {
			label = "cbtinfo";
			reg = <0x6180000 0x80000>;
			read-only;
		};
		/* seems to be the end here. Can't read past 0x6200000 */
	};
};

&pcie {
	status = "okay";
};

&pcie1 {
	wifi@0,0 {
		compatible = "mediatek,mt76";
		reg = <0x0000 0 0 0 0>;
		mediatek,mtd-eeprom = <&factory 0x0000>;
	};
};

&state_default {
	gpio {
		groups = "i2c", "uart3", "jtag", "wdt";
		function = "gpio";
	};
};

&gmac1 {
	status = "okay";
	label = "wan";
	phy-handle = <&ethphy0>;
};

&mdio {
	ethphy0: ethernet-phy@0 {
		reg = <0>;
	};
};

&switch0 {
	gpio-controller;
	#gpio-cells = <2>;

	ports {
		port@1 {
			status = "okay";
			label = "lan4";
		};

		port@2 {
			status = "okay";
			label = "lan3";
		};

		port@3 {
			status = "okay";
			label = "lan2";
		};

		port@4 {
			status = "okay";
			label = "lan1";
		};
	};
};




DTS for Similar Device on Kernel 5.5 which has openwrt support(2):

// SPDX-License-Identifier: GPL-2.0-or-later

#include "mt7621.dtsi"

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>

/ {
	compatible = "tplink,eap615-wall-v1", "mediatek,mt7621-soc";
	model = "TP-Link EAP615-Wall v1";

	aliases {
		label-mac-device = &gmac0;
		led-boot = &led_status;
		led-failsafe = &led_status;
		led-running = &led_status;
		led-upgrade = &led_status;
	};

	chosen {
		bootargs = "console=ttyS0,115200";
	};

	leds {
		compatible = "gpio-leds";

		led_status: status {
			label = "white:status";
			color = <LED_COLOR_ID_WHITE>;
			function = LED_FUNCTION_STATUS;
			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
		};
	};

	keys {
		compatible = "gpio-keys";

		led {
			label = "led";
			gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_LIGHTS_TOGGLE>;
		};

		reset {
			label = "reset";
			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_RESTART>;
		};
	};

	gpio-export {
		compatible = "gpio-export";

		poe_passthrough {
			gpio-export,name = "poe-passthrough";
			gpio-export,output = <0>;
			gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
		};
	};
};

&ethernet {
	reg = <0x1e100000 0xe000>;
};

&spi0 {
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <20000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "u-boot";
				reg = <0x0 0x80000>;
				read-only;
			};

			partition@80000 {
				label = "partition-table";
				reg = <0x80000 0x10000>;
				read-only;
			};

			info: partition@90000 {
				label = "product-info";
				reg = <0x90000 0x10000>;
				read-only;
			};

			partition@a0000 {
				compatible = "denx,fit";
				label = "firmware";
				reg = <0xa0000 0xcf0000>;
			};

			partition@d90000 {
				label = "user-config";
				reg = <0xd90000 0x60000>;
				read-only;
			};

			partition@f30000 {
				label = "mutil-log";
				reg = <0xf30000 0x80000>;
				read-only;
			};

			partition@fb0000 {
				label = "oops";
				reg = <0xfb0000 0x40000>;
				read-only;
			};

			radio: partition@ff0000 {
				label = "radio";
				reg = <0xff0000 0x10000>;
				read-only;
			};
		};
	};
};

&state_default {
	gpio {
		groups = "uart2", "uart3";
		function = "gpio";
	};
};

&pcie {
	status = "okay";
};

&pcie1 {
	wifi@0,0 {
		compatible = "mediatek,mt76";
		reg = <0x0000 0 0 0 0>;
		mediatek,mtd-eeprom = <&radio 0x0>;
		mediatek,disable-radar-background;
	};
};

&gmac0 {
	nvmem-cells = <&macaddr_info_8>;
	nvmem-cell-names = "mac-address";
};

&gmac1 {
	status = "okay";
	label = "lan0";
	phy-handle = <&ethphy0>;

	nvmem-cells = <&macaddr_info_8>;
	nvmem-cell-names = "mac-address";
};

&mdio {
	ethphy0: ethernet-phy@0 {
		reg = <0>;
	};
};

&switch0 {
	ports {
		port@1 {
			status = "okay";
			label = "lan3";
		};

		port@2 {
			status = "okay";
			label = "lan2";
		};

		port@3 {
			status = "okay";
			label = "lan1";
		};
	};
};

&info {
	compatible = "nvmem-cells";
	#address-cells = <1>;
	#size-cells = <1>;

	macaddr_info_8: macaddr@8 {
		reg = <0x8 0x6>;
	};
};

Any help or pointers would be greatly appreciated!

Thank you in advance.

don't bother with 5.5, openwrt and ramips is already at 6.6.

Okay, my issue is wifi driver is not loading as eeprom load fails.

&pcie1 {
    wifi@0,0 {
        compatible = "mediatek,mt76";
        reg = <0x0000 0 0 0 0>;
        mediatek,mtd-eeprom = <&factory 0x0>;
    };
};

this is being done in most of the similar devices which has exact specs for initializing WiFi from dts. Do you have any suggestions for helping me with this? Thanks in advance:)

Is there really an EEPROM at this location? Dump the content of the factory partition and check if the required EEPROM data is there.

1 Like

Thanks for your reply. you were right there was nothing like EEPROM when i dumped factory partition.

root@OpenWrt:/tmp# hexdump -C factory_dump.bin
00000000 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................|
* 

this was the output. Now I changed the partition structure to something like this.

&spi0 {
    status = "okay";

    flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0>;
        spi-max-frequency = <10000000>;
        broken-flash-reset;

        partitions {
            compatible = "fixed-partitions";
            #address-cells = <1>;
            #size-cells = <1>;

            partition@0 {
                label = "Bootloader";
                reg = <0x0 0x30000>;
            };

            partition@30000 {
                label = "Config";
                reg = <0x30000 0x10000>;
            };

            factory: partition@40000 {
                label = "Factory";
                reg = <0x40000 0x40000>;
            };

	    firmware: partition@90000 {
    		label = "firmware";
    		reg = <0x90000 0xF70000>;
	    };

	    kernel: partition@9f0000 {
    		label = "kernel";
    		reg = <0x9f0000 0x340000>;
	    };

            rootfs: partition@3d0000 {
                label = "rootfs";
                reg = <0x3d0000 0xc30000>;
            };

            rootfs_data: partition@b20000 {
                label = "rootfs_data";
                reg = <0xb20000 0x4e0000>;
            };
        };
    };
};

Now I figured out the EEPROM location by assuming some mac address found in factory dump. Changed the location in pcie1 initialization and now I got my WiFi working. Thanks for your help once again!

You can identify the EEPROM area by looking at the magic values, i.e. the expected start bytes. What to expect can be found in the mt76 source code (I don't know of any documentation, although there might be some).

Okay, Thank you for letting me know.

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