Captured communication between STC8 a d PoE board. Prococol looks really weird. The are two data lines, but no one can be interpolated as SCL for I2C communication. It have some data exchange every 2 sec.
Will attach collected sample tomorrow.
In case someone finds it useful, below is a firmware update for the RTL9303 based Hasivo F1100WP-4XS-4XGT. It contains an i2c-poe.ko kernel module that might be interesting to reverse engineer, for instance.
Do you really mean between STC8 and PoE board (with HS104PTI chips)?
or do you mean between Realtek SoC and STC8?
I don’t think we’d care much about what communication occurs between STC8 and PoE board. Only what ‘our chip’ (the Realtek SoC) needs to say to the STC8 to get the right PoE operations occuring.
What PoE chips are in use on this F1100WP-4XS-4XGT? We do already have the I2C Register Map for the HS104 chips, so there’s likely no benefit to reverse engineering that module if it’s for the HS104 chips. We’d be better just writing our own driver against mainline linux PSE standards for it (which I’ve got… but untested currently).
Yeah. I mean exactly that. And you are right it is more important to captured communication between RTL and STC8.
Fwiw, I yolo installed the S1100W-8XGT-SE firmware on my S1100WP-8XGT-SE and PoE has been working fine for months without a proper driver.
I believe they use the same PoE board in all their switches. The specs are certainly the same from what I can tell. I just figured the kernel module might have some value in case their PoE board had some quirks or something that wasn't immediately obvious. 
It's also the first firmware update I've seen for this switch available in the wild, so I figured that might also make it interesting to some. 
Sorry if this is not for the right place to ask, but is it possible to flash S1100W-8XGT-SE into F1100W-4SX-4XGT? I think they shared the 9303 part, where 4 SFP+ is directed connected to 9303, and 4 RJ45 10G using RTL8264?
@bevanweiss Thx for your effort you put into this to make it work ...
I was wondering if you or some other folks have already a branch on git that has a commit with your latest tryouts?
I started to compile a image for S1100WP-8GT-SE ... with mdio and booted it via ymodem, which works. (rtk network on ...not) I was tinkering a little around with gpio and and different dts configs. But I am far away of bringing up an interface on any network speed.
best,
@bevanweiss ,Is that your latest tryout? https://github.com/bevanweiss/openwrt/commit/d195029a3e632b182e3f9b74d406f28bd8347c20
with that version the kernel detects no physical interfaces at all and no lan ports are shown up... hmm
Negative.
I just haven’t pushed to github lately.
There’s still issues with the interfaces not actually passing traffic in my testing (at 1Gbps), which is likely because UBoot doesn’t correctly initialise them and OpenWRT doesn’t fully initialise them either (relying on the bootloader having mostly set them up).
@bevanweiss one of the fans in my S1100WP-8XGT-SE died and sounds like an angle grinder. I’ve got it fully disassembled until the new fans arrive tomorrow. Is there anything in regard to the PoE chip you want tested before then?
Hi @plappermaul,
Would you mind sharing some ideas were you would start to debug deeper?
I have downloaded the original firmware from the device and could go into some reverse engineering, but from what I read this seems to be not really helpful.
I can't believe that the hasivo guys added some complicated custom stuff to initialize - especially when other devices like S1100W-8XGT-SE work with openwrt and opensource drivers without special adjustment. Hasivo has 10-20 different switches with different network hardware and building for every device workarounds would cost them way too much effort. So my uneducated guess is that they keep it rather simple... The serdes, mdio (smi) config, link detection seems to work for me as well, same as @bevanweiss wrote.
What would yo do if you have the hardware? Where would you add more debug output to the driver? Which steps would you perform?
I totally would appreciate some ideas where to start as there are very few articles online to read...
Maybe other experts may help as well ... like @andrewjlamarche @bevanweiss @janh
Totally appreciated!
To make a long story short. To get a port up and running you need:
- The PHY (RTL82xx) must be initialized properly including its SerDes towards the SoC
- The SerDes in the SoC where the PHY is attached to, must be initialized properly
- The link between SerDes and PHY must show "up" on both sides.
In case of the S1100WP-8GT-SE we have 8x RTL8221B individually attached to one of the 12 SerDes of the RTL930x. I assume their link type should be 2500baseX.
To check how far OpenWrt initializes all this, have a look at the SerDes and PHY registers to verify if that this mode is really enabled.
- In case of the PHY use the mdio bus
- In case of the SerDes look at debugfs/realtek_serdes/XX/registers
For more details see:
- _dal_longan_sds_mode_get()
- dal_longan_sds_linkSts_get()
- RTL8221B datasheet SERDES Control 3 Register (MMD 30.0x7580)
And do not forget that Jonas is working hard on the PCS driver to get the SerDes stuff up and running.
Thx for your quick reply @plappermaul Cool!
If Jonas is working on it, would you recommend just wait for him to finish - especially as I am no expert... Maybe he reads this thread and shares some feedback as well.
My config is the following (openwrt main branch 1-2 weeks old)
&mdio_bus0 {
phy0: ethernet-phy@0 {
reg = <0>;
compatible = "ethernet-phy-ieee802.3-c45";
rtl9300,smi-address = <0 1>;
};
...
}
&switch0 {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
phy-handle = <&phy0>;
phy-mode = "2500base-x";
led-set = <0>;
pcs-handle = <&serdes2>;
};
...
/* Internal SoC */
port@28 {
ethernet = <ðernet0>;
reg = <28>;
phy-mode = "internal";
fixed-link {
speed = <10000>;
full-duplex;
};
};
};
Using SerDes 2-9, I got from Sven Heule.
boot:
[ 36.640856] rtl838x-eth 1b00a300.ethernet eth0: Link is Down
[ 37.271538] Using MAC 00000028241338b5
[ 37.276419] RESETTING 9300, CPU_PORT 28
[ 37.488317] rtl838x-eth 1b00a300.ethernet eth0: configuring for fixed/internal link mode
[ 37.497361] In rtl838x_mac_config, mode 1
[ 37.502391] rtl838x-eth 1b00a300.ethernet eth0: Link is Up - 1Gbps/Full - flow control off
[ 37.525995] rtl83xx-switch switch@1b000000 lan1: configuring for phy/2500base-x link mode
[ 37.535210] realtek-otto-pcs 1b000000.switchcore:pcs: pcs_config(2500base-x) for port 0 and sds 2 not yet fully impld
[ 37.547835] rtpcs_930x_sds_set 31 serd
[ 37.564199] rtpcs_930x_phy_enable_10g_1g 1gbit phy: 00000140
[ 37.570684] rtpcs_930x_phy_enable_10g_1g 1gbit phy enabled: 00000140
[ 37.577938] rtpcs_930x_phy_enable_10g_1g 10gbit phy: 00002040
[ 37.584419] rtpcs_930x_phy_enable_10g_1g 10gbit phy after: 00002040
[ 37.591652] rtpcs_930x_phy_enable_10g_1g set medium: 00000002
[ 37.598221] rtpcs_930x_phy_enable_10g_1g set medium after: 00000002
[ 37.605268] rtpcs_930x_setup_serdes: Configuring RTL9300 SERDES 2
[ 37.612321] rtpcs_930x_sds_config_pll: SDS 2 using LC PLL for 2500base-x
[ 37.667450] rtpcs_930x_sds_10g_idle WARNING: Waiting for RX idle timed out, SDS 2
[ 37.675961] start_1.1.1 initial value for sds 2
[ 37.681238] end_1.1.1 --
[ 37.684099] start_1.1.2 Load DFE init. value
[ 37.689164] end_1.1.2
[ 37.691737] start_1.1.3 disable LEQ training,enable DFE clock
[ 37.698385] end_1.1.3 --
[ 37.701254] start_1.1.4 offset cali setting
[ 37.706143] end_1.1.4
[ 37.708711] start_1.1.5 LEQ and DFE setting
[ 37.713418] rtpcs_930x_sds_do_rx_calibration_1 not PHY-based or SerDes, implement DAC!
[ 37.722494] end_1.1.5
[ 37.731189] start_1.2.1 ForegroundOffsetCal_Manual
[ 37.736753] end_1.2.1
[ 37.742758] start_1.2.3 Foreground Calibration
[ 37.750512] rtpcs_930x_sds_do_rx_calibration_2_3: fgcal_gray: 31, fgcal_binary 31
[ 37.759054] rtpcs_930x_sds_do_rx_calibration_2_3: end_1.2.3
[ 37.765317] start_1.4.1
[ 38.003061] end_1.4.1
[ 38.005927] start_1.4.2
[ 38.009520] vth_set_bin = 7
[ 38.012249] vth_set_bin = 3
[ 38.015352] Vth Maunal = 0
[ 38.120224] Tap0 Sign : +
[ 38.123267] tap0_coef_bin = 31
[ 38.126328] tap0 manual = 0
[ 38.129784] end_1.4.2
[ 38.203243] rtpcs_930x_sds_sym_err_reset unsupported phy mode
[ 38.212274] rtpcs_930x_sds_sym_err_reset unsupported phy mode
[ 38.218794] rtpcs_930x_sds_sym_err_get unsupported PHY-mode
[ 38.226164] rtpcs_930x_sds_sym_err_get unsupported PHY-mode
[ 38.232395] start_1.1.1 initial value for sds 2
[ 38.237678] end_1.1.1 --
[ 38.240529] start_1.1.2 Load DFE init. value
[ 38.245306] end_1.1.2
[ 38.247967] start_1.1.3 disable LEQ training,enable DFE clock
[ 38.254432] end_1.1.3 --
[ 38.257386] start_1.1.4 offset cali setting
[ 38.262101] end_1.1.4
[ 38.264646] start_1.1.5 LEQ and DFE setting
[ 38.269408] rtpcs_930x_sds_do_rx_calibration_1 not PHY-based or SerDes, implement DAC!
[ 38.278475] end_1.1.5
[ 38.286199] start_1.2.1 ForegroundOffsetCal_Manual
[ 38.291588] end_1.2.1
[ 38.296736] start_1.2.3 Foreground Calibration
[ 38.304239] rtpcs_930x_sds_do_rx_calibration_2_3: fgcal_gray: 31, fgcal_binary 31
[ 38.312706] rtpcs_930x_sds_do_rx_calibration_2_3: end_1.2.3
[ 38.319055] start_1.4.1
[ 38.539901] end_1.4.1
[ 38.542649] start_1.4.2
[ 38.546398] vth_set_bin = 7
[ 38.549144] vth_set_bin = 3
[ 38.552249] Vth Maunal = 0
[ 38.656904] Tap0 Sign : +
[ 38.659946] tap0_coef_bin = 31
[ 38.662859] tap0 manual = 0
[ 38.666412] end_1.4.2
[ 38.739858] rtpcs_930x_sds_sym_err_reset unsupported phy mode
[ 38.748839] rtpcs_930x_sds_sym_err_reset unsupported phy mode
[ 38.755244] rtpcs_930x_sds_sym_err_get unsupported PHY-mode
[ 38.762705] rtpcs_930x_sds_sym_err_get unsupported PHY-mode
- I was checking the mdio bus and I get link detection with correct speed:
rtl83xx-switch switch@1b000000 lan1: Link is Up - 100Mbps/Half - flow control off
or
rtl83xx-switch switch@1b000000 lan1: Link is Up - 1Gbps/Full - flow control rx/tx
- The added debug log appears often:
[13545.397236] rtl822xb_update_interface backend SerDes of PHY 0 running in SGMII
[13546.437161] rtl822xb_update_interface backend SerDes of PHY 0 running in SGMII
[13547.477149] rtl822xb_update_interface backend SerDes of PHY 0 running in SGMII
- mdio to the device works:
root@OpenWrt:/sys/kernel/debug/realtek_otto_serdes# phytool read lan1/0/0x01
0x0002 -> no link
root@OpenWrt:/sys/kernel/debug/realtek_otto_serdes# phytool read lan1/0/0x02
0x001c
root@OpenWrt:/sys/kernel/debug/realtek_otto_serdes# phytool read lan1/0/0x03
0xc849
root@OpenWrt:/sys/kernel/debug/realtek_otto_serdes# phytool read lan1/0/0x04
root@OpenWrt:/sys/kernel/debug/realtek_otto_serdes# phytool read lan1/0/0x01
0x0006 -> link up
I assume 0x04 is about the speed, PMA/PMD Speed Ability Register (MMD 1.0x0004 , referring to the 8221B datasheed, If I am not wrong...
- Regarding the SerDes, I dumped the register output:
root@OpenWrt:/sys/kernel/debug/realtek_otto_serdes# cat serdes.2/registers
Back SDS 02: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
SDS : 1403 0F00 70D0 3106 0749 8E00 8F5F 1359 524B F000 8BA4 0000 08E4 4636 3053 0000 0000 0000 0000 4001 0001 4001 9800 9800 001C 001C 3804 0000 C040 001F 0000 0000
SDS_EXT : FFFF FF00 FFFF FF00 0000 0000 0000 0003 283F 4000 0000 0000 0004 326A 0332 1162 2ABD 0000 0000 0000 0100 0000 0000 0000 0010 02BC 0000 0000 0000 0101 0101 0000
FIB : 0140 6109 3380 02A0 01A0 0000 0000 0004 0000 0000 0000 0000 0000 0000 0000 8000 0083 0000 5000 0000 0000 0000 0001 4001 0004 326A 0000 115D 33FA E46A 071E 0000
FIB_EXT : 1140 6109 3380 02A0 01A0 0000 0000 0004 0000 0000 0000 0000 0000 0000 0000 8000 02D6 0000 0124 031B 1F33 6002 0000 1408 0000 1005 0001 0000 0000 0000 0000 0000
DTE : 2040 0004 0000 0000 0001 002A 0000 0000 8001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
DTE_EXT : 000C 8000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
TGX : 0000 C800 0000 445C 6EAA E1A8 6473 2303 7670 0000 0000 0000 0000 0F00 015A 5A5A 432E 00A8 00A4 7690 F047 E6C4 65C5 A29B 3D79 8040 0000 0000 0000 0000 0000 0000
TGX_EXT : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1711 1516 783F 60AA 054F 0FFF 0FFF 0FFF 6318 0006 0000 0000 0000 0001 0000 0021 0FFF FB05 0000
ANA_RG : 2040 0000 0000 0000 0001 0028 0000 0000 8000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0010 0000 0000 0000 0800 0000 0000 0000 0000 0000 0000 0000
ANA_RG_EXT : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
ANA_TG : 0007 0300 8000 0000 0000 0000 B6B5 0000 0000 0000 0000 0000 0000 0000 0332 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
ANA_TG_EXT : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 0C : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0003 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 0D : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 0E : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 0F : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 10 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 11 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 12 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 13 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 14 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 15 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 16 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 17 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 18 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 19 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 1A : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 1B : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 1C : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 1D : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 1E : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
ANA_WDIG : 0000 0000 002F 0000 0000 0000 0C04 DC05 0603 0140 0000 0002 A05A 0708 0001 0000 0000 0000 0000 0000 001F 3000 885F 0000 0000 0000 0000 0000 0000 0000 0000 0000
ANA_MISC : 0030 0000 0000 0000 A05A 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 13DF 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
ANA_COM : 0000 FFFF 03C0 8206 F0F0 40B0 0810 F09F 0000 FFFF 0003 0007 0007 6009 0000 0008 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
ANA_SP : 0668 2088 D020 5F5F 08C0 1000 C000 4820 23FF F000 1000 1892 2427 0BFF 0000 FFDF 2BFF 8280 03C4 027F 1311 60C1 00C9 A100 BE48 0000 0001 FFFF 0400 0000 07F8 8888
ANA_SP_EXT : 820F 0B00 1017 FFDF 0000 7F7C 0201 8099 0001 FFD4 7C2F 7C07 0000 0000 003F 0121 0020 8840 0000 0050 2008 8000 4000 4109 8E88 4902 A02B 0003 1109 2641 6430 3024
ANA_1G : 0668 2088 D020 5F5F 08C0 1000 C000 4820 23FF F000 1000 1892 2427 0BFF 0000 FFDF 2BFF 8280 03C4 027F 1311 60C1 00C9 A100 BE48 0000 0001 FFFF 0400 0000 07F8 8888
ANA_1G_EXT : 820F 0B00 1017 FFDF 0000 7F7C 0201 8099 0001 FFD4 7C2F 7C07 0000 0000 003F 0121 0020 8840 0000 0034 2008 8000 4000 4105 8F88 490A A02B 0003 7109 2500 5030 2624
ANA_2G : 8360 2088 F020 5F5F 08C0 1000 E000 4820 23FF F000 1000 188A 2427 0BFF 0000 BFDF 2BFF 8280 0084 227F 2179 60C1 00CB 0100 BE48 0000 0000 FFFF 4400 0000 07F8 8888
ANA_2G_EXT : 820F 0100 1107 FFD0 0000 787C 0200 8104 0003 FFC4 7C4F 7C07 0000 0000 FFFF F8A1 0028 8030 0000 0034 2008 8000 4000 4105 8F88 490A A02B 0003 7109 2500 5030 2624
ANA_3G : 0668 2088 D020 5F5F 08C0 1000 C000 4820 23FF F000 1000 1892 2427 0BFF 0000 FFDF 2BFF 8280 01C4 027F 1311 60C1 00C9 A100 BE48 0000 0001 FFFF 0400 0000 07F8 8888
ANA_3G_EXT : 820F 0300 1017 FFDF 0000 7F7C 0208 8100 0001 FFD4 7C2F 7C07 0000 0000 003F 0121 0020 8840 0000 0034 2008 8000 4000 4105 8F88 490A A02B 0003 7109 2640 6430 3024
ANA_5G : 8360 2088 F020 5F5F 08C0 1000 E000 4820 23FF F000 1000 188A 2427 0BFF 0000 BFDF 2BFF 8280 0084 227F 2179 60C1 00CB 0100 BE48 0000 0000 FFFF 4400 0000 07F8 8888
ANA_5G_EXT : 820F 0100 1107 FFD0 0000 787C 0200 8104 0003 FFC4 7C4F 7C07 0000 0000 FFFF F8A1 0028 8030 0000 0050 2008 8000 4000 4105 8E88 4902 A02B 0003 7109 2501 5030 2624
ANA_6G : 8360 2088 F020 5F5F 08C0 1000 E000 4820 23FF F000 1000 188A 2427 0BFF 0000 BFDF 2BFF 8280 0084 227F 2179 60C1 00CB 0100 BE48 0000 0000 FFFF 4400 0000 07F8 8888
ANA_6G_EXT : 820F 0100 1107 FFD0 0000 787C 0200 8104 0003 FFC4 7C4F 7C07 0000 0000 FFFF F8A1 0028 8030 0000 0050 2008 8000 4000 4109 8E88 4902 A02B 0003 1109 2641 6430 3024
ANA_10G : A668 2088 D020 5F5F 08C0 1000 C000 4820 23FF F000 1000 1893 2427 0BFF 0000 FFDF 2BFF 8280 0044 027B 1311 62C1 00CB A100 BE48 03E0 0001 FFFF 0400 0000 07F8 8888
ANA_10G_EXT: 820F 0300 1217 FFDF 0000 7F7C 0200 80C4 0001 FFD4 7C2F 7807 0000 0000 003F 0121 0020 8840 0000 0050 E008 8000 4000 4104 8E88 4902 A12B 0003 7109 76E1 6E30 3524
PAGE 30 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 31 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 32 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 33 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 34 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 35 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 36 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 37 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 38 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 39 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 3A : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 3B : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 3C : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 3D : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 3E : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
PAGE 3F : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
I guess I need to understand if the SerDes detects the devices as "up" and if the speed matches to decode ?
What is also interesting that ANA_SP is not equal to ANA_2G.
I will go deeper here soon: I assume https://github.com/openwrt/openwrt/pull/20062/files helps to understand.
- Can you give another hint how the realtek code could help me (dal_longan_sds) ?
Tomorrow more...
Regarding the link of the PHY:
- There is a frontend/LAN link -> message "lanX Link is up"
- There is a backend/SoC link -> no messages until now
With the SDK code and your output, we can read the SerDes mode of the SoC
/* get mode from serdes */
if ((ret = SDS_FIELD_R(unit, sds, 0x1f, 9, 11, 7, &value)) != RT_ERR_OK)
Page 0x1f (ANA_WDIG), register 0x9 reads 0x0140 and bits 7-11 give 2. With
case 0x2:
*pMode = RTK_MII_SGMII;
break;
This tells us, that the SerDes is running in SGMII. From your output (Link is Up - 1Gbps/Full) this is the right mode as the PHY dynamically switches its backend SerDes mode. See https://elixir.bootlin.com/linux/v6.18.2/source/drivers/net/phy/realtek/realtek_main.c#L1313
So fine until here. Now look at the link between PHY and SerDes. We use this SDK code.
else
{
RT_ERR_HDL(SDS_FIELD_R(unit, sds, 0x1, 29, 8, 0, &info->sts), ERR, ret);
RT_ERR_HDL(SDS_FIELD_R(unit, sds, 0x1, 30, 8, 0, &info->latch_sts), ERR, ret);
}
Sadly your register output misses the info about page 1 (SDS_EXT) register 29 (0x1d) and bits 0-8. So you have to look yourself. From my experience I expect there to be 9 times an active 1-bit.
I remember there was some discussion about 1G modes not working on RTL8221B. The predecessor RTL8226 does that fine. Maybe @Borromini remebers better.
Do not wait for @jonasj work. Neither he nor me has access to a RTL8221B based device. We must rely on your support.
Amazing, I haven't expected a reply so fast @plappermaul
Sorry for the missing bytes, ... I did not recognize it! I updated the code block, so it includes the missing registers: page 1, register 29 is 0x0101 while link is up at 1G.
As simple as this:
- 0x1fff = Link fully up
- 0x101 = something failed.
The PHY SerDes and the SoC SerDes are not linked properly.
In this case there are some options:
- SoC SerDes needs initialization -> should be more or less in place
- The PHY needs initialization -> not in place. SDK provides https://github.com/plappermaul/realtek-doc/tree/main/sources/rtk-dms1250/src/hal/phy/nic_rtl8226