Well it should be 1 as it is the only PHY.
but all devices are memory mapped, as far as I understand. Or how else are they connected to the CPU?
Hm,we really need to discuss that.
There is a full datasheet for MT7621 but no mention on memory or PHY adress for the RGMII interface
Pls see my link that I sent before with the pin out of AR8033. It shows also the PHY Address: 5b'00000
It's noted below the Media modes.
I took a look at it today.
I know how it works now.
They are using the port5 of the switch to make a RGMII interface to the AR8033.
Datasheet confirms that.
Port5 should be set as GMAC5
https://github.com/openwrt/openwrt/blob/master/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/gsw_mt7621.c#L117
I'm not actually convinced that AR8033 is connected to the switch. It may communicate directly with the CPU.
So far, i tried the following, but AG71XX does not seem to be present in the kernel. It booted without any indication of ag71xx:
diff --git a/target/linux/ramips/dts/UBNT-ERX-SFP.dts b/target/linux/ramips/dts/UBNT-ERX-SFP.dts
index 7de3780..f891c8f 100644
--- a/target/linux/ramips/dts/UBNT-ERX-SFP.dts
+++ b/target/linux/ramips/dts/UBNT-ERX-SFP.dts
@@ -21,4 +21,12 @@
reg = <0x25>;
};
};
+
+ eth1: ethernet@5b00000 {
+ compatible = "ag71xx";
+ status = "okay";
+ phy-mode = "rgmii";
+ };
+
};
+
diff --git a/target/linux/ramips/mt7621/config-4.14 b/target/linux/ramips/mt7621/config-4.14
index 3a5cd42..3f7596a 100644
--- a/target/linux/ramips/mt7621/config-4.14
+++ b/target/linux/ramips/mt7621/config-4.14
@@ -284,3 +284,4 @@ CONFIG_WEAK_ORDERING=y
CONFIG_XPS=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
+CONFIG_AG71XX=y
ag71xx is the driver for built in phys and switches in qca MIPS.
Try using at803x but you need to enable building it in config.
Also,please dont use eth1 label.
sfp would be much better.
But I think that there is also pinmux needed and clocks for RGMII
Okay, where do we find the reference doc for the bit flags?
Ie, which bit toggles enable state, or media mode?
Have been searching a bit, but can't find any docs about MT7530 switch or the MT7621 for that matter. Can find some datasheets, but they're wiring diagrams, as in hardware, not specific software functions, constants etc, so we know how to apply correct pinmux, clock settings.
If I understand robimarko right, the MT7530 port 5 serves as a bridge to AR8033 using RGMII int. So all communication to it is accepted by AR8033. Which made it pretty difficult for us to understand how it's wired all together.
Question to me is more, does than port 5 work as a transparant bridge to the AR8033 PHY?
If I m telling merely mumbojumbo, feel free to correct me.
I got some hints from Robi, and will try to implement them in a quick and dirty fashion over the weekend. If it works, it will need proper armoring with #ifdeffs and stuff.
Guys,you have MT7621 full datasheet avaialable:
You can find the pinmux for RGMII there,also MDIO and MDC pins needed
Also "mt7621 programmer guide" is easy to google. The forum didn't allow me to upload a PDF.
also this looks relevant: https://www.kernel.org/doc/Documentation/devicetree/bindings/net/dsa/mt7530.txt
val &= ~(1<<8);
This should enable port6 since the code is the same as MT7620 and there is a comment that it enables port6
Take a look at this
so far, enabling Port 5 on the switch did not help. swconfig still shows port 5 down. Also at803x is not visible in kernel messages. I can't find any relevant documentation for mt7530. Maybe something else needs to be enabled.
diff --git a/target/linux/ramips/dts/UBNT-ERX-SFP.dts b/target/linux/ramips/dts/UBNT-ERX-SFP.dts
index 7de3780..01d74ec 100644
--- a/target/linux/ramips/dts/UBNT-ERX-SFP.dts
+++ b/target/linux/ramips/dts/UBNT-ERX-SFP.dts
@@ -21,4 +21,12 @@
reg = <0x25>;
};
};
+
+ eth1: ethernet@5b00000 {
+ compatible = "at803x";
+ status = "okay";
+ phy-mode = "rgmii";
+ };
+
};
+
diff --git a/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/gsw_mt7621.c b/target/linux/ramips/files-4.14/drivers/net/ether
index 9d5fe6e..3685d2f 100644
--- a/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/gsw_mt7621.c
+++ b/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/gsw_mt7621.c
@@ -116,8 +116,10 @@ static void mt7621_hw_init(struct mt7620_gsw *gsw, struct device_node *np)
/* Enable Port 6, P5 as GMAC5, P5 disable */
val = mt7530_mdio_r32(gsw, 0x7804);
- val &= ~BIT(8);
- val |= BIT(6) | BIT(13) | BIT(16);
+ val &= ~BIT(8); /* Enable Port 6 */
+ val &= ~BIT(6); /* Enable Port 5 */
+ val |= BIT(13); /* Port 5 as GMAC, no Internal PHY */
+ val |= BIT(16); /* change HW-TRAP */
mt7530_mdio_w32(gsw, 0x7804, val);
val = rt_sysc_r32(0x10);
diff --git a/target/linux/ramips/mt7621/config-4.14 b/target/linux/ramips/mt7621/config-4.14
index 3a5cd42..512fe08 100644
--- a/target/linux/ramips/mt7621/config-4.14
+++ b/target/linux/ramips/mt7621/config-4.14
@@ -284,3 +284,4 @@ CONFIG_WEAK_ORDERING=y
CONFIG_XPS=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
+CONFIG_AT803X_PHY=y
looks like I need to set bits 15:14 (GE2_MODE) to zeros. Will try it now
1 Like
Did it work?
nope. I also copied the GE2 initialization code from GE1 initialization, but without proper documentation on mt7530, it's just mumbo-jumbo:
diff --git a/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/gsw_mt7621.c b/target/linux/ramips/files-4.14/drivers/net/ether
index 9d5fe6e..e656df5 100644
--- a/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/gsw_mt7621.c
+++ b/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/gsw_mt7621.c
@@ -84,6 +84,9 @@ static void mt7621_hw_init(struct mt7620_gsw *gsw, struct device_node *np)
/* set GMAC1 RGMII mode */
rt_sysc_m32(3 << 12, 0, SYSC_REG_CFG1);
+ /* set GMAC2 RGMII mode */
+ rt_sysc_m32(3 << 14, 0, SYSC_REG_CFG1);
+
/* enable MDIO to control MT7530 */
rt_sysc_m32(3 << 12, 0, SYSC_GPIO_MODE);
@@ -109,15 +112,20 @@ static void mt7621_hw_init(struct mt7620_gsw *gsw, struct device_node *np)
}
/* (GE2, Link down) */
- mtk_switch_w32(gsw, 0x8000, GSW_REG_MAC_P1_MCR);
-
+ /* mtk_switch_w32(gsw, 0x8000, GSW_REG_MAC_P1_MCR); */
+ mtk_switch_w32(gsw, 0x2305e33b, GSW_REG_MAC_P1_MCR);
+ mt7530_mdio_w32(gsw, 0x8000, 0x5e33b);
+ printk("the cake is a lie\n");
+
/* Set switch max RX frame length to 2k */
mt7530_mdio_w32(gsw, GSW_REG_GMACCR, 0x3F0B);
/* Enable Port 6, P5 as GMAC5, P5 disable */
val = mt7530_mdio_r32(gsw, 0x7804);
- val &= ~BIT(8);
- val |= BIT(6) | BIT(13) | BIT(16);
+ val &= ~BIT(8); /* Enable Port 6 */
+ val &= ~BIT(6); /* Enable Port 5 */
+ val |= BIT(13); /* Port 5 as GMAC, no Internal PHY */
+ val |= BIT(16); /* change HW-TRAP */
mt7530_mdio_w32(gsw, 0x7804, val);
val = rt_sysc_r32(0x10);
Take a look at this PR
https://github.com/openwrt/openwrt/pull/703
It has AR8035 PHY connected over RGMII and there is a lot of stuff to configure
Found documentation for programming the switch.