I've just finished the install and it is quite late over here but I can do that tomorrow evening. Thanks for your hard work in getting OpenWrt to work on this device.
No worries, when you have time as I find it rather weird that suddenly switch doesnt work properly only on this device
Thx for your info.!
I got the OEM (OTA) firmware image on this thread by it seems not valid to extract UBI image by using your provide instructions.
The original OTA image name is Dynalink-RT5010W-d350-V1.10.01.201_sysupgrade_firmware_wififw.bin and I rename it to oem_firmware.bin
below is the output when I reun dumpimage:
fw$ dumpimage -l ./oem_firmware.bin
GP Header: Size d00dfeed LoadAddr 2d20aa4
fw$ dumpimage -T flat_dt -p 0 -o dynalink-dl-wrx36.oem.ubi oem_firmware.bin
dumpimage: failed to verify header of FIT Image support
dumpimage: Can't extract subimage from oem_firmware.bin
It seems the OTA firmware is not a FIT image.
Any suggestion for me to make it work?
Or would you pls. send me your OEM UBI file instead?
Are you sure you have the right OEM firmware?
Taking the one from this post on the thread I got the following:
# md5sum Dynalink-RT5010W-d350-V1.10.01.201_sysupgrade_firmware_wififw.bin
c368dbf24e24df16d61b97a40feb5a92 Dynalink-RT5010W-d350-V1.10.01.201_sysupgrade_firmware_wififw.bin
# dumpimage -l Dynalink-RT5010W-d350-V1.10.01.201_sysupgrade_firmware_wififw.bin
Image contains unit addresses @, this will break signing
FIT description: Dynalink_RT5010W-D350 Sysupgrade_Image 1.10.01.201
Created: Wed Mar 23 16:05:07 2022
Image 0 (askey-rootfs)
Description: rt5010w-d350-ubi-root.img
Created: Wed Mar 23 16:05:07 2022
Type: Firmware
Compression: uncompressed
Data Size: 42729472 Bytes = 41728.00 KiB = 40.75 MiB
Architecture: ARM
OS: Unknown OS
Load Address: unavailable
Hash algo: crc32
Hash value: 64531456
Image 1 (wififw_v1-rt5010w)
Description: rt5010w-d350-ubi-wififw.img
Created: Wed Mar 23 16:05:07 2022
Type: Firmware
Compression: uncompressed
Data Size: 2097152 Bytes = 2048.00 KiB = 2.00 MiB
Architecture: ARM
OS: Unknown OS
Load Address: unavailable
Hash algo: crc32
Hash value: daa41489
Image 2 (wififw_v2-rt5010w)
Description: rt5010w-d350-ubi-wififw_v2.img
Created: Wed Mar 23 16:05:07 2022
Type: Firmware
Compression: uncompressed
Data Size: 2490368 Bytes = 2432.00 KiB = 2.38 MiB
Architecture: ARM
OS: Unknown OS
Load Address: unavailable
Hash algo: crc32
Hash value: a5d44389
# dumpimage -T flat_dt -p 0 -o dynalink-dl-wrx36.oem.ubi Dynalink-RT5010W-d350-V1.10.01.201_sysupgrade_firmware_wififw.bin
Image contains unit addresses @, this will break signing
Extracted:
Image 0 (askey-rootfs)
Description: rt5010w-d350-ubi-root.img
Created: Wed Mar 23 16:05:07 2022
Type: Firmware
Compression: uncompressed
Data Size: 42729472 Bytes = 41728.00 KiB = 40.75 MiB
Architecture: ARM
OS: Unknown OS
Load Address: unavailable
Hash algo: crc32
Hash value: 64531456
Please check you have the same file (md5sum matches).
If you do, maybe it's related to the dumpimage version.
I'm using 2022.10 on Arch Linux from uboot-tools package.
2 Likes
My MD5 checksum are same as you!
Let me try another version of dumpimage and update you later.
THX!
Update the dumpimage version to 2022.10 work!!
I'm able to extract the UBI image now!
Confirm your provided method is work!
I'm able to restore to factory firmware without any issues!
THX!
1 Like
for you 
root@OpenWrt:/# cat /sys/kernel/debug/clk/clk_summary
enable prepare protect duty hardware
clock count count count rate accuracy phase cycle enable
-------------------------------------------------------------------------------------------------------
uniphy2_gcc_tx_clk 1 1 0 312500000 0 0 50000 Y
nss_port6_tx_clk_src 1 1 0 78125000 0 0 50000 Y
nss_port6_tx_div_clk_src 2 2 0 6009616 0 0 50000 Y
gcc_uniphy2_port6_tx_clk 1 1 0 6009616 0 0 50000 Y
gcc_nss_port6_tx_clk 1 1 0 6009616 0 0 50000 Y
uniphy2_gcc_rx_clk 1 1 0 312500000 0 0 50000 Y
nss_port6_rx_clk_src 1 1 0 78125000 0 0 50000 Y
nss_port6_rx_div_clk_src 2 2 0 6009616 0 0 50000 Y
gcc_uniphy2_port6_rx_clk 1 1 0 6009616 0 0 50000 Y
gcc_nss_port6_rx_clk 1 1 0 6009616 0 0 50000 Y
uniphy1_gcc_tx_clk 0 0 0 125000000 0 0 50000 Y
uniphy1_gcc_rx_clk 0 0 0 125000000 0 0 50000 Y
uniphy0_gcc_tx_clk 5 5 0 125000000 0 0 50000 Y
nss_port1_tx_clk_src 1 1 0 25000000 0 0 50000 Y
nss_port1_tx_div_clk_src 2 2 0 2500000 0 0 50000 Y
gcc_uniphy0_port1_tx_clk 1 1 0 2500000 0 0 50000 Y
gcc_nss_port1_tx_clk 1 1 0 2500000 0 0 50000 Y
nss_port2_tx_clk_src 1 1 0 25000000 0 0 50000 Y
nss_port2_tx_div_clk_src 2 2 0 2500000 0 0 50000 Y
gcc_uniphy0_port2_tx_clk 1 1 0 2500000 0 0 50000 Y
gcc_nss_port2_tx_clk 1 1 0 2500000 0 0 50000 Y
nss_port3_tx_clk_src 1 1 0 25000000 0 0 50000 Y
nss_port3_tx_div_clk_src 2 2 0 2500000 0 0 50000 Y
gcc_uniphy0_port3_tx_clk 1 1 0 2500000 0 0 50000 Y
gcc_nss_port3_tx_clk 1 1 0 2500000 0 0 50000 Y
nss_port4_tx_clk_src 1 1 0 25000000 0 0 50000 Y
nss_port4_tx_div_clk_src 2 2 0 2500000 0 0 50000 Y
gcc_uniphy0_port4_tx_clk 1 1 0 2500000 0 0 50000 Y
gcc_nss_port4_tx_clk 1 1 0 2500000 0 0 50000 Y
nss_port5_tx_clk_src 1 1 0 25000000 0 0 50000 Y
nss_port5_tx_div_clk_src 3 3 0 2500000 0 0 50000 Y
gcc_uniphy1_port5_tx_clk 1 1 0 2500000 0 0 50000 Y
gcc_uniphy0_port5_tx_clk 1 1 0 2500000 0 0 50000 Y
gcc_nss_port5_tx_clk 1 1 0 2500000 0 0 50000 Y
uniphy0_gcc_rx_clk 5 5 0 125000000 0 0 50000 Y
nss_port1_rx_clk_src 1 1 0 25000000 0 0 50000 Y
nss_port1_rx_div_clk_src 2 2 0 2500000 0 0 50000 Y
gcc_uniphy0_port1_rx_clk 1 1 0 2500000 0 0 50000 Y
gcc_nss_port1_rx_clk 1 1 0 2500000 0 0 50000 Y
nss_port2_rx_clk_src 1 1 0 25000000 0 0 50000 Y
nss_port2_rx_div_clk_src 2 2 0 2500000 0 0 50000 Y
gcc_uniphy0_port2_rx_clk 1 1 0 2500000 0 0 50000 Y
gcc_nss_port2_rx_clk 1 1 0 2500000 0 0 50000 Y
nss_port3_rx_clk_src 1 1 0 25000000 0 0 50000 Y
nss_port3_rx_div_clk_src 2 2 0 2500000 0 0 50000 Y
gcc_uniphy0_port3_rx_clk 1 1 0 2500000 0 0 50000 Y
gcc_nss_port3_rx_clk 1 1 0 2500000 0 0 50000 Y
nss_port4_rx_clk_src 1 1 0 25000000 0 0 50000 Y
nss_port4_rx_div_clk_src 2 2 0 2500000 0 0 50000 Y
gcc_uniphy0_port4_rx_clk 1 1 0 2500000 0 0 50000 Y
gcc_nss_port4_rx_clk 1 1 0 2500000 0 0 50000 Y
nss_port5_rx_clk_src 1 1 0 25000000 0 0 50000 Y
nss_port5_rx_div_clk_src 3 3 0 2500000 0 0 50000 Y
gcc_uniphy1_port5_rx_clk 1 1 0 2500000 0 0 50000 Y
gcc_uniphy0_port5_rx_clk 1 1 0 2500000 0 0 50000 Y
gcc_nss_port5_rx_clk 1 1 0 2500000 0 0 50000 Y
gcc_usb0_pipe_clk_src 0 0 0 125000000 0 0 50000 Y
bias_pll_nss_noc_clk 1 1 0 416500000 0 0 50000 Y
nss_noc_bfdcd_clk_src 1 1 0 416500000 0 0 50000 Y
nss_noc_clk_src 2 2 0 416500000 0 0 50000 Y
gcc_ubi1_nc_axi_clk 0 0 0 416500000 0 0 50000 N
gcc_ubi1_axi_clk 0 0 0 416500000 0 0 50000 N
gcc_ubi0_nc_axi_clk 0 0 0 416500000 0 0 50000 N
gcc_ubi0_axi_clk 0 0 0 416500000 0 0 50000 N
gcc_nss_noc_clk 1 1 0 416500000 0 0 50000 Y
gcc_mem_noc_nss_axi_clk 1 1 0 416500000 0 0 50000 Y
bias_pll_cc_clk 1 1 0 300000000 0 0 50000 Y
nss_ppe_clk_src 15 15 0 300000000 0 0 50000 Y
gcc_crypto_ppe_clk 0 0 0 300000000 0 0 50000 N
gcc_port6_mac_clk 1 1 0 300000000 0 0 50000 Y
gcc_port5_mac_clk 1 1 0 300000000 0 0 50000 Y
gcc_port4_mac_clk 1 1 0 300000000 0 0 50000 Y
gcc_port3_mac_clk 1 1 0 300000000 0 0 50000 Y
gcc_port2_mac_clk 1 1 0 300000000 0 0 50000 Y
gcc_port1_mac_clk 1 1 0 300000000 0 0 50000 Y
gcc_nssnoc_ppe_clk 1 1 0 300000000 0 0 50000 Y
gcc_nssnoc_ppe_cfg_clk 1 1 0 300000000 0 0 50000 Y
gcc_nss_ppe_ipe_clk 1 1 0 300000000 0 0 50000 Y
gcc_nss_ppe_clk 1 1 0 300000000 0 0 50000 Y
gcc_nss_ppe_cfg_clk 1 1 0 300000000 0 0 50000 Y
gcc_nss_ppe_btq_clk 1 1 0 300000000 0 0 50000 Y
gcc_nss_edma_clk 1 1 0 300000000 0 0 50000 Y
gcc_nss_edma_cfg_clk 1 1 0 300000000 0 0 50000 Y
nss_ppe_cdiv_clk_src 1 1 0 75000000 0 0 50000 Y
gcc_nss_ptp_ref_clk 1 1 0 75000000 0 0 50000 Y
xo 10 10 0 19200000 0 0 50000 Y
usb0_mock_utmi_clk_src 1 1 0 19200000 0 0 55555 Y
gcc_usb0_mock_utmi_clk 1 1 0 19200000 0 0 50000 Y
a53pll 1 1 0 1382400000 0 0 50000 Y
apcs_alias0_clk_src 1 1 0 1382400000 0 0 50000 Y
apcs_alias0_core_clk 1 1 0 1382400000 0 0 50000 Y
gp3_clk_src 0 0 0 19200000 0 0 50000 N
gcc_gp3_clk 0 0 0 19200000 0 0 50000 N
gp2_clk_src 0 0 0 19200000 0 0 50000 N
gcc_gp2_clk 0 0 0 19200000 0 0 50000 N
gp1_clk_src 0 0 0 19200000 0 0 50000 N
gcc_gp1_clk 0 0 0 19200000 0 0 50000 N
ubi_mpt_clk_src 0 0 0 19200000 0 0 50000 N
gcc_ubi1_mpt_clk 0 0 0 19200000 0 0 50000 N
gcc_ubi0_mpt_clk 0 0 0 19200000 0 0 50000 N
nss_ubi1_clk_src 0 0 0 19200000 0 0 50000 N
nss_ubi1_div_clk_src 0 0 0 19200000 0 0 50000 Y
gcc_ubi1_core_clk 0 0 0 19200000 0 0 50000 N
nss_ubi0_clk_src 0 0 0 19200000 0 0 50000 N
nss_ubi0_div_clk_src 0 0 0 19200000 0 0 50000 Y
gcc_ubi0_core_clk 0 0 0 19200000 0 0 50000 N
gcc_xo_clk_src 5 5 0 19200000 0 0 50000 Y
gcc_uniphy2_sys_clk 1 1 0 19200000 0 0 50000 Y
gcc_uniphy1_sys_clk 1 1 0 19200000 0 0 50000 Y
gcc_uniphy0_sys_clk 1 1 0 19200000 0 0 50000 Y
gcc_cmn_12gpll_sys_clk 1 1 0 19200000 0 0 50000 Y
gcc_nssnoc_qosgen_ref_clk 0 0 0 19200000 0 0 50000 N
gcc_xo_div4_clk_src 0 0 0 4800000 0 0 50000 Y
gcc_nssnoc_timeout_ref_clk 0 0 0 4800000 0 0 50000 N
usb1_aux_clk_src 0 0 0 19200000 0 0 50000 N
gcc_usb1_aux_clk 0 0 0 19200000 0 0 50000 N
usb0_aux_clk_src 1 1 0 19200000 0 0 50000 Y
gcc_usb0_aux_clk 1 1 0 19200000 0 0 50000 Y
sdcc2_apps_clk_src 0 0 0 19200000 0 0 50000 N
gcc_sdcc2_apps_clk 0 0 0 19200000 0 0 50000 N
sdcc1_apps_clk_src 0 0 0 19200000 0 0 50000 N
gcc_sdcc1_apps_clk 0 0 0 19200000 0 0 50000 N
pcie1_aux_clk_src 0 0 0 19200000 0 0 50000 N
gcc_pcie1_aux_clk 0 0 0 19200000 0 0 50000 N
pcie0_aux_clk_src 0 0 0 19200000 0 0 50000 N
gcc_pcie0_aux_clk 0 0 0 19200000 0 0 50000 N
nss_crypto_pll_main 1 1 0 1190400000 0 0 50000 Y
nss_crypto_pll 1 1 0 595200000 0 0 50000 Y
nss_crypto_clk_src 1 1 0 595200000 0 0 50000 Y
gcc_nssnoc_crypto_clk 0 0 0 595200000 0 0 50000 N
gcc_nss_crypto_clk 1 1 0 595200000 0 0 50000 Y
ubi32_pll_main 0 0 0 1497600000 0 0 50000 N
ubi32_pll 0 0 0 1497600000 0 0 50000 Y
gpll6_main 1 1 0 1080000000 0 0 50000 Y
gpll6 0 0 0 1080000000 0 0 50000 Y
usb1_mock_utmi_clk_src 0 0 0 20000000 0 0 55555 Y
gcc_usb1_mock_utmi_clk 0 0 0 20000000 0 0 50000 N
sdcc1_ice_core_clk_src 0 0 0 308571428 0 0 50000 N
gcc_sdcc1_ice_core_clk 0 0 0 308571428 0 0 50000 N
gpll6_out_main_div2 0 0 0 540000000 0 0 50000 Y
gpll4_main 1 1 0 1200000000 0 0 50000 Y
gpll4 0 0 0 1200000000 0 0 50000 Y
gpll2_main 1 1 0 1152000000 0 0 50000 Y
gpll2 0 0 0 1152000000 0 0 50000 Y
blsp1_uart6_apps_clk_src 0 0 0 19200000 0 0 50000 N
gcc_blsp1_uart6_apps_clk 0 0 0 19200000 0 0 50000 N
blsp1_uart4_apps_clk_src 0 0 0 19200000 0 0 50000 N
gcc_blsp1_uart4_apps_clk 0 0 0 19200000 0 0 50000 N
blsp1_uart3_apps_clk_src 0 0 0 19200000 0 0 50000 N
gcc_blsp1_uart3_apps_clk 0 0 0 19200000 0 0 50000 N
blsp1_uart2_apps_clk_src 0 0 0 19200000 0 0 50000 N
gcc_blsp1_uart2_apps_clk 0 0 0 19200000 0 0 50000 N
blsp1_uart1_apps_clk_src 0 0 0 19200000 0 0 50000 N
gcc_blsp1_uart1_apps_clk 0 0 0 19200000 0 0 50000 N
gpll0_main 1 1 0 800000000 0 0 50000 Y
gpll0_out_main_div2 0 0 0 400000000 0 0 50000 Y
gpll0 6 6 0 800000000 0 0 50000 Y
crypto_clk_src 1 1 0 160000000 0 0 50000 Y
gcc_crypto_clk 1 1 0 160000000 0 0 50000 Y
nss_imem_clk_src 1 1 0 400000000 0 0 50000 Y
gcc_nss_imem_clk 1 1 0 400000000 0 0 50000 Y
system_noc_bfdcd_clk_src 2 2 0 266666666 0 0 50000 Y
system_noc_clk_src 1 1 0 266666666 0 0 50000 Y
gcc_nssnoc_snoc_clk 1 1 0 266666666 0 0 50000 Y
usb1_master_clk_src 0 0 0 133333333 0 0 50000 Y
gcc_usb1_master_clk 0 0 0 133333333 0 0 50000 N
gcc_sys_noc_usb1_axi_clk 0 0 0 133333333 0 0 50000 N
usb0_master_clk_src 2 2 0 133333333 0 0 50000 Y
gcc_usb0_master_clk 1 1 0 133333333 0 0 50000 Y
gcc_sys_noc_usb0_axi_clk 1 1 0 133333333 0 0 50000 Y
pcie1_axi_clk_src 0 0 0 200000000 0 0 50000 N
gcc_sys_noc_pcie1_axi_clk 0 0 0 200000000 0 0 50000 N
gcc_pcie1_axi_s_clk 0 0 0 200000000 0 0 50000 N
gcc_pcie1_axi_m_clk 0 0 0 200000000 0 0 50000 N
pcie0_axi_clk_src 0 0 0 200000000 0 0 50000 N
gcc_pcie0_axi_s_bridge_clk 0 0 0 200000000 0 0 50000 N
gcc_sys_noc_pcie0_axi_clk 0 0 0 200000000 0 0 50000 N
gcc_pcie0_axi_s_clk 0 0 0 200000000 0 0 50000 N
gcc_pcie0_axi_m_clk 0 0 0 200000000 0 0 50000 N
pcnoc_bfdcd_clk_src 2 2 0 100000000 0 0 50000 Y
pcnoc_clk_src 12 12 0 100000000 0 0 50000 Y
gcc_crypto_axi_clk 1 1 0 100000000 0 0 50000 Y
gcc_crypto_ahb_clk 1 2 0 100000000 0 0 50000 Y
gcc_uniphy2_ahb_clk 1 1 0 100000000 0 0 50000 Y
gcc_uniphy1_ahb_clk 1 1 0 100000000 0 0 50000 Y
gcc_uniphy0_ahb_clk 1 1 0 100000000 0 0 50000 Y
gcc_mdio_ahb_clk 2 2 0 100000000 0 0 50000 Y
gcc_cmn_12gpll_ahb_clk 1 1 0 100000000 0 0 50000 Y
gcc_nss_cfg_clk 0 0 0 100000000 0 0 50000 N
gcc_sdcc2_ahb_clk 0 0 0 100000000 0 0 50000 N
gcc_sdcc1_ahb_clk 0 0 0 100000000 0 0 50000 N
gcc_usb1_phy_cfg_ahb_clk 0 0 0 100000000 0 0 50000 N
gcc_usb0_phy_cfg_ahb_clk 2 2 0 100000000 0 0 50000 Y
gcc_pcie1_ahb_clk 0 0 0 100000000 0 0 50000 N
gcc_pcie0_ahb_clk 0 0 0 100000000 0 0 50000 N
gcc_qpic_clk 1 1 0 100000000 0 0 50000 Y
gcc_qpic_ahb_clk 1 2 0 100000000 0 0 50000 Y
gcc_prng_ahb_clk 1 1 0 100000000 0 0 50000 Y
gcc_blsp1_ahb_clk 3 4 0 100000000 0 0 50000 N
blsp1_uart5_apps_clk_src 1 1 0 3686400 0 0 50003 Y
gcc_blsp1_uart5_apps_clk 3 3 0 3686400 0 0 50000 Y
blsp1_qup6_spi_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup6_spi_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup6_i2c_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup6_i2c_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup5_spi_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup5_spi_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup5_i2c_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup5_i2c_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup4_spi_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup4_spi_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup4_i2c_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup4_i2c_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup3_spi_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup3_spi_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup3_i2c_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup3_i2c_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup2_spi_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup2_spi_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup2_i2c_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup2_i2c_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup1_spi_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup1_spi_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup1_i2c_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup1_i2c_apps_clk 0 0 0 50000000 0 0 50000 N
sleep_clk 2 2 0 32768 0 0 50000 Y
gcc_sleep_clk_src 2 2 0 32768 0 0 50000 Y
gcc_usb1_sleep_clk 0 0 0 32768 0 0 50000 N
gcc_usb0_sleep_clk 1 1 0 32768 0 0 50000 Y
pcie0_rchng_clk_src 0 0 0 0 0 0 50000 N
gcc_pcie0_rchng_clk 0 0 0 0 0 0 50000 N
nss_ce_clk_src 0 0 0 0 0 0 50000 N
gcc_ubi1_ahb_clk 0 0 0 0 0 0 50000 N
gcc_ubi0_ahb_clk 0 0 0 0 0 0 50000 N
gcc_nssnoc_ubi1_ahb_clk 0 0 0 0 0 0 50000 N
gcc_nssnoc_ubi0_ahb_clk 0 0 0 0 0 0 50000 N
gcc_nssnoc_ce_axi_clk 0 0 0 0 0 0 50000 N
gcc_nssnoc_ce_apb_clk 0 0 0 0 0 0 50000 N
gcc_nss_csr_clk 0 0 0 0 0 0 50000 N
gcc_nss_ce_axi_clk 0 0 0 0 0 0 50000 N
gcc_nss_ce_apb_clk 0 0 0 0 0 0 50000 N
usb1_pipe_clk_src 0 0 0 0 0 0 50000 Y
gcc_usb1_pipe_clk 0 0 0 0 0 0 50000 N
usb0_pipe_clk_src 1 1 0 0 0 0 50000 Y
gcc_usb0_pipe_clk 1 1 0 0 0 0 50000 Y
pcie1_pipe_clk_src 0 0 0 0 0 0 50000 Y
gcc_pcie1_pipe_clk 0 0 0 0 0 0 50000 N
pcie0_pipe_clk_src 0 0 0 0 0 0 50000 Y
gcc_pcie0_pipe_clk 0 0 0 0 0 0 50000 N
root@OpenWrt:/#
with the build from 17.12.2022
Hm, clocks look quite broken but nothing has really changed in a long time.
Cause, I have just upgraded my Dynalink to the latest build and clocks look like they should at 125MHz for 1G.
Those crazy values were a bug, but its been fixed for a while now
What is the version you are running?
1 Like
root@OpenWrt:/# cat /proc/version
Linux version 5.15.83 (robimarko@fedora) (aarch64-openwrt-linux-musl-gcc (OpenWrt GCC 11.3.0 r0-8a3812b) 11.3.0, GNU ld (GNU Binutils) 2.37) #0 SMP Fri Dec 16 16:51:58 2022
Now it makes no sense for me, so you are saying that WAN port works but others dont?
no... no Port is working after
tftpboot openwrt-ipq807x-generic-dynalink_dl-wrx36-initramfs-fit-uImage.itb
bootm
now i will test it with this version... or do you need more???
https://github.com/robimarko/openwrt/releases/download/ipq807x-2022-08-18/openwrt-ipq807x-generic-dynalink_dl-wrx36-initramfs-fit-uImage.itb
Whats the issue if it works?
I dont care about that version from 4 months ago at all
no... no Port is working
so now i flash with this itb
https://github.com/robimarko/openwrt/releases/download/ipq807x-2022-08-18/openwrt-ipq807x-generic-dynalink_dl-wrx36-initramfs-fit-uImage.itb
and all is working now... thanks to all
...
bevore i test it with the " 9594846" build...
and it won´t work!
That is extremely weird, cause I am using the latest version as my home AP and its working fine.
Version from August isn't really the solution.
i need the old version only to get it work... for wired connection
to transfer the new firmware by SCP...
now it runs with the newest build...
(this time i create one with FW.2.7 to test)
So, it works when flashed but not when booted as initramfs?
yes exactly this!
Oh, that is a new one, I have had stuff not work after flashing but work fine in initramfs as bootloader would initialize them, but not this.
I would help if I could...
but I'm a noob in this...
so if i can test something i will do this to go it work!