Hello everyone, that´s my first Post here, so Hi Community 
unluckily i bricked already 2 of my TL-WPA8631P in the attempt of making them RADIUS-able....
I used them at first with just Stock Openwrt version 23.05.2/23.05.3 precompiled, but unfortunately it got only wpad-basic-mbedtls instead of a full fledged wpad. So i looked around and found the imagebuilder... well after a lot of struggle figuring out the usage and especially about how to really getting rid of wpad-basic-mbedtls (PACKAGE= -wpad-basic-mbedtls didn´t work) which wasn´t an easy task i got it running on the device.
Well i should have stopped here and everything would have been fine but i tried to free a bit more memory in flash for a slightly larger overlayfs and in an attempt to get rid of the firewall i messed up...
Device behavior is now all LED´s flashing and after a while all LED´s switch off completely.
I already looked into the De-bricking sections of several devices and got good progress but i feel i´m at a point where i really could use some help....
Luckily my Devices still answer over a Serial Connection via a Raspberry PI so i got into U-Boot and tried re-flashing several binaries (via tftp), stock / self compiled all to no-avail.
Got a copy of a Log for reference, it didn´t matter which version i uploaded the result is always the same...
Uncompressing Kernel Image ... LZMA ERROR 1 - must RESET board to recover
===================================================================
MT7621 stage1 code Mar 12 2015 14:43:30 (ASIC)
CPU=500000000 HZ BUS=125000000 HZ
==================================================================
Change MPLL source from XTAL to CR...
do MEMPLL setting..
MEMPLL Config : 0x11000000
3PLL mode + External loopback
=== XTAL-40Mhz === DDR-800Mhz ===
PLL2 FB_DL: 0xc, 1/0 = 598/426 31000000
PLL3 FB_DL: 0x16, 1/0 = 532/492 59000000
PLL4 FB_DL: 0x1e, 1/0 = 598/426 79000000
do DDR setting..[01F40000]
Apply DDR2 Setting...(use default AC)
0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120
--------------------------------------------------------------------------------
0000:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0001:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0002:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0003:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0004:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0005:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0006:| 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
0007:| 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
0008:| 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0
0009:| 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
000A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0010:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0011:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0012:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0013:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0014:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0015:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0016:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0017:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0018:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0019:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DRAMC_DQSCTL1[0e0]=1A000000
DRAMC_DQSGCTL[124]=80000000
rank 0 coarse = 8
rank 0 fine = 48
B:| 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0
opt_dle value:7
DRAMC_DDR2CTL[07c]=40001273
DRAMC_PADCTL4[0e4]=00000005
DRAMC_DQIDLY1[210]=0C0D0A0A
DRAMC_DQIDLY2[214]=080B0B0B
DRAMC_DQIDLY3[218]=0B090807
DRAMC_DQIDLY4[21c]=07090903
DRAMC_R0DELDLY[018]=00002B2B
==================================================================
RX DQS perbit delay software calibration
==================================================================
1.0-15 bit dq delay value
==================================================================
bit| 0 1 2 3 4 5 6 7 8 9
--------------------------------------
0 | 9 7 11 11 9 9 11 6 5 6
10 | 9 9 1 7 5 6
--------------------------------------
==================================================================
2.dqs window
x=pass dqs delay value (min~max)center
y=0-7bit DQ of every group
input delay:DQS0 =43 DQS1 = 43
==================================================================
bit DQS0 bit DQS1
0 (3~81)42 8 (1~82)41
1 (1~79)40 9 (1~82)41
2 (2~81)41 10 (1~86)43
3 (1~83)42 11 (0~83)41
4 (1~82)41 12 (0~82)41
5 (1~82)41 13 (1~81)41
6 (3~83)43 14 (0~79)39
7 (1~81)41 15 (2~83)42
==================================================================
3.dq delay value last
==================================================================
bit| 0 1 2 3 4 5 6 7 8 9
--------------------------------------
0 | 10 10 13 12 11 11 11 8 7 8
10 | 9 11 3 9 9 7
==================================================================
==================================================================
TX perbyte calibration
==================================================================
DQS loop = 15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqsdly_pass[0]=15, finish count=1
dqs_perbyte_dly.last_dqsdly_pass[1]=15, finish count=2
DQ loop=15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqdly_pass[0]=15, finish count=1
dqs_perbyte_dly.last_dqdly_pass[1]=15, finish count=2
byte:0, (DQS,DQ)=(8,8)
byte:1, (DQS,DQ)=(8,8)
DRAMC_DQODLY1[200]=88888888
DRAMC_DQODLY2[204]=88888888
20,data:88
[EMI] DRAMC calibration passed
===================================================================
MT7621 stage1 code done
CPU=500000000 HZ BUS=125000000 HZ
===================================================================
U-Boot 1.1.3 (Jul 28 2023 - 15:17:31)
Board: Ralink APSoC DRAM: 64 MB
relocate_code Pointer at: 83fb8000
Config XHCI 40M PLL
******************************
Software System Reset Occurred
******************************
flash manufacture id: 20, device id 40 17
Warning: un-recognized chip ID, please update bootloader!
*** Warning - bad CRC, using default environment
===========================TL-WPA8631Pv3 PERSET GPIO init in uboot=========================
read register GPIO_MODE(0xbe000060), value = 0x0004d52c
set register GPIO_MODE(0xbe000060), value = 0x0004d52c
read register GPIO_CTRL_0(0xbe000600), value = 0x35c00000
set register GPIO_CTRL_0(0xbe000600), value = 0x35c80000
read register GPIO_DATA_0(0xbe000620), value = 0xc83de81e
set register GPIO_DATA_0(0xbe000620), value = 0xc835e81e
=========================TL-WPA8631Pv3 PERSET GPIO init in uboot done==========================
============================================
Ralink UBoot Version: 4.3.0.0
--------------------------------------------
ASIC MT7621A DualCore (MAC to MT7530 Mode)
DRAM_CONF_FROM: Auto-Detection
DRAM_TYPE: DDR2
DRAM bus: 16 bit
Xtal Mode=3 OCP Ratio=1/4
Flash component: SPI Flash
Date:Jul 28 2023 Time:15:17:31
============================================
icache: sets:256, ways:4, linesz:32 ,total:32768
dcache: sets:256, ways:4, linesz:32 ,total:32768
##### The CPU freq = 880 MHZ ####
estimate memory size =64 Mbytes
#Reset_MT7530
=========TL-WPA8631Pv3 GPIO init in uboot=========
RALINK_PIO_BASE(0xbe000600) Reg: 0x4852c
RALINK_PIO_BASE + 4(0xbe000604) Reg: 0x0
RALINK_GPIOMODE_REG(0xbe000060) Reg: 0x4852c
=========TL-WPA8631Pv3 GPIO init in uboot done=========
Please choose the operation:
1: Load system code to SDRAM via TFTP.
2: Load system code then write to Flash via TFTP.
3: Boot system code via Flash (default).
4: Entr boot command line interface.
7: Load Boot Loader code then write to Flash via Serial.
9: Load Boot Loader code then write to Flash via TFTP.
You choosed 2
0
2: System Load Linux Kernel then write to Flash via TFTP.
Warning!! Erase Linux in Flash then burn new one. Are you sure?(Y/N)
Please Input new ones /or Ctrl-C to discard
Input device IP (192.168.0.254) ==:192.168.0.254
Input server IP (192.168.0.184) ==:192.168.0.184
Input Linux Kernel filename () ==:test.bin
netboot_common, argc= 3
NetTxPacket = 0x83FE5600
KSEG1ADDR(NetTxPacket) = 0xA3FE5600
NetLoop,call eth_halt !
NetLoop,call eth_init !
Trying Eth0 (10/100-M)
Waitting for RX_DMA_BUSY status Start... done
ETH_STATE_ACTIVE!!
TFTP from server 192.168.0.184; our IP address is 192.168.0.254
Filename 'test.bin'.
TIMEOUT_COUNT=10,Load address: 0x80100000
Loading: *Got ARP REPLY, set server/gtwy eth addr (3c:7c:3f:c3:58:92)
Got it
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
######################Got ARP REQUEST, return our IP
###########################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
##########################################
done
Bytes transferred = 6869736 (68d2e8 hex)
NetBootFileXferSize= 0068d2e8
........................................................................................................
raspi_write 1179: to:20000 len:680000
........................................................................................................
.
raspi_write 1179: to:6a0000 len:10000
.
Done!
## Booting image at bfc20000 ...
text base: ffffffff
entry point: ffffffff
Uncompressing Kernel Image ... LZMA ERROR 1 - must RESET board to recover
===================================================================
MT7621 stage1 code Mar 12 2015 14:43:30 (ASIC)
CPU=500000000 HZ BUS=125000000 HZ
==================================================================
Change MPLL source from XTAL to CR...
do MEMPLL setting..
MEMPLL Config : 0x11000000
3PLL mode + External loopback
=== XTAL-40Mhz === DDR-800Mhz ===
PLL2 FB_DL: 0xc, 1/0 = 591/433 31000000
PLL3 FB_DL: 0x15, 1/0 = 547/477 55000000
PLL4 FB_DL: 0x1e, 1/0 = 653/371 79000000
do DDR setting..[01F40000]
Apply DDR2 Setting...(use default AC)
0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120
--------------------------------------------------------------------------------
0000:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0001:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0002:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0003:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0004:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0005:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0006:| 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
0007:| 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
0008:| 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0
0009:| 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
000A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0010:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0011:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0012:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0013:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0014:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0015:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0016:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0017:| 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
0018:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0019:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DRAMC_DQSCTL1[0e0]=1A000000
DRAMC_DQSGCTL[124]=80000000
rank 0 coarse = 8
rank 0 fine = 48
B:| 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0
opt_dle value:5
DRAMC_DDR2CTL[07c]=40001253
DRAMC_PADCTL4[0e4]=00000005
DRAMC_DQIDLY1[210]=0D0D0A0A
DRAMC_DQIDLY2[214]=080B0C0B
DRAMC_DQIDLY3[218]=0B090708
DRAMC_DQIDLY4[21c]=07080903
DRAMC_R0DELDLY[018]=00002B2B
==================================================================
RX DQS perbit delay software calibration
==================================================================
1.0-15 bit dq delay value
==================================================================
bit| 0 1 2 3 4 5 6 7 8 9
--------------------------------------
0 | 9 7 11 11 9 9 11 6 5 6
10 | 9 10 1 7 5 6
--------------------------------------
==================================================================
2.dqs window
x=pass dqs delay value (min~max)center
y=0-7bit DQ of every group
input delay:DQS0 =43 DQS1 = 43
==================================================================
bit DQS0 bit DQS1
0 (3~81)42 8 (1~80)40
1 (1~79)40 9 (1~83)42
2 (2~81)41 10 (1~85)43
3 (1~82)41 11 (1~83)42
4 (1~82)41 12 (1~81)41
5 (1~80)40 13 (1~81)41
6 (3~83)43 14 (1~80)40
7 (1~81)41 15 (2~82)42
==================================================================
3.dq delay value last
==================================================================
bit| 0 1 2 3 4 5 6 7 8 9
--------------------------------------
0 | 10 10 13 13 11 12 11 8 8 7
10 | 9 11 3 9 8 7
==================================================================
==================================================================
TX perbyte calibration
==================================================================
DQS loop = 15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqsdly_pass[0]=15, finish count=1
dqs_perbyte_dly.last_dqsdly_pass[1]=15, finish count=2
DQ loop=15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqdly_pass[0]=15, finish count=1
dqs_perbyte_dly.last_dqdly_pass[1]=15, finish count=2
byte:0, (DQS,DQ)=(8,8)
byte:1, (DQS,DQ)=(8,8)
DRAMC_DQODLY1[200]=88888888
DRAMC_DQODLY2[204]=88888888
20,data:88
[EMI] DRAMC calibration passed
===================================================================
MT7621 stage1 code done
CPU=500000000 HZ BUS=125000000 HZ
===================================================================
U-Boot 1.1.3 (Jul 28 2023 - 15:17:31)
Board: Ralink APSoC DRAM: 64 MB
relocate_code Pointer at: 83fb8000
Config XHCI 40M PLL
******************************
Software System Reset Occurred
******************************
flash manufacture id: 20, device id 40 17
Warning: un-recognized chip ID, please update bootloader!
*** Warning - bad CRC, using default environment
===========================TL-WPA8631Pv3 PERSET GPIO init in uboot=========================
read register GPIO_MODE(0xbe000060), value = 0x0004d52c
set register GPIO_MODE(0xbe000060), value = 0x0004d52c
read register GPIO_CTRL_0(0xbe000600), value = 0x35c00000
set register GPIO_CTRL_0(0xbe000600), value = 0x35c80000
read register GPIO_DATA_0(0xbe000620), value = 0xc83de81e
set register GPIO_DATA_0(0xbe000620), value = 0xc835e81e
=========================TL-WPA8631Pv3 PERSET GPIO init in uboot done==========================
============================================
Ralink UBoot Version: 4.3.0.0
--------------------------------------------
ASIC MT7621A DualCore (MAC to MT7530 Mode)
DRAM_CONF_FROM: Auto-Detection
DRAM_TYPE: DDR2
DRAM bus: 16 bit
Xtal Mode=3 OCP Ratio=1/4
Flash component: SPI Flash
Date:Jul 28 2023 Time:15:17:31
============================================
icache: sets:256, ways:4, linesz:32 ,total:32768
dcache: sets:256, ways:4, linesz:32 ,total:32768
##### The CPU freq = 880 MHZ ####
estimate memory size =64 Mbytes
#Reset_MT7530
=========TL-WPA8631Pv3 GPIO init in uboot=========
RALINK_PIO_BASE(0xbe000600) Reg: 0x4852c
RALINK_PIO_BASE + 4(0xbe000604) Reg: 0x0
RALINK_GPIOMODE_REG(0xbe000060) Reg: 0x4852c
=========TL-WPA8631Pv3 GPIO init in uboot done=========
Please choose the operation:
1: Load system code to SDRAM via TFTP.
2: Load system code then write to Flash via TFTP.
3: Boot system code via Flash (default).
4: Entr boot command line interface.
7: Load Boot Loader code then write to Flash via Serial.
9: Load Boot Loader code then write to Flash via TFTP.
0
3: System Boot system code via Flash.
(ntohs(targetModel[0]) : 0x0376, ntohs(value[0]) : 0x0376
(ntohs(targetModel[1]) : 0x6376, ntohs(value[1]) : 0x6376
## Booting image at bfc20000 ...
text base: ffffffff
entry point: ffffffff
Uncompressing Kernel Image ... LZMA ERROR 1 - must RESET board to recover
===================================================================
MT7621 stage1 code Mar 12 2015 14:43:30 (ASIC)
CPU=500000000 HZ BUS=125000000 HZ
==================================================================
Change MPLL source from XTAL to CR...
do MEMPLL setting..
MEMPLL Config : 0x11000000
3PLL mode + External loopback
=== XTAL-40Mhz === DDR-800Mhz ===
PLL2 FB_DL: 0xc, 1/0 = 576/448 31000000
PLL3 FB_DL: 0x15, 1/0 = 515/509 55000000
PLL4 FB_DL: 0x1d, 1/0 = 539/485 75000000
do DDR setting..[01F40000]
Apply DDR2 Setting...(use default AC)
0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120
--------------------------------------------------------------------------------
0000:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0001:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0002:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0003:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0004:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0005:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0006:| 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
0007:| 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
0008:| 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0
0009:| 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
000A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0010:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0011:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0012:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0013:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0014:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0015:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0016:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0017:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0018:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0019:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DRAMC_DQSCTL1[0e0]=1A000000
DRAMC_DQSGCTL[124]=80000000
rank 0 coarse = 8
rank 0 fine = 48
B:| 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0
opt_dle value:7
DRAMC_DDR2CTL[07c]=40001273
DRAMC_PADCTL4[0e4]=00000005
DRAMC_DQIDLY1[210]=0C0C0A0B
DRAMC_DQIDLY2[214]=080B0B0B
DRAMC_DQIDLY3[218]=0B090706
DRAMC_DQIDLY4[21c]=07080803
DRAMC_R0DELDLY[018]=00002A2B
==================================================================
RX DQS perbit delay software calibration
==================================================================
1.0-15 bit dq delay value
==================================================================
bit| 0 1 2 3 4 5 6 7 8 9
--------------------------------------
0 | 9 7 11 11 9 9 11 6 5 6
10 | 9 10 1 7 6 5
--------------------------------------
==================================================================
2.dqs window
x=pass dqs delay value (min~max)center
y=0-7bit DQ of every group
input delay:DQS0 =43 DQS1 = 42
==================================================================
bit DQS0 bit DQS1
0 (3~80)41 8 (1~81)41
1 (1~79)40 9 (1~81)41
2 (2~82)42 10 (1~84)42
3 (1~83)42 11 (1~82)41
4 (1~82)41 12 (0~81)40
5 (1~81)41 13 (1~81)41
6 (3~83)43 14 (1~80)40
7 (1~82)41 15 (0~81)40
==================================================================
3.dq delay value last
==================================================================
bit| 0 1 2 3 4 5 6 7 8 9
--------------------------------------
0 | 11 10 12 12 11 11 11 8 6 7
10 | 9 11 3 8 8 7
==================================================================
==================================================================
TX perbyte calibration
==================================================================
DQS loop = 15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqsdly_pass[0]=15, finish count=1
dqs_perbyte_dly.last_dqsdly_pass[1]=15, finish count=2
DQ loop=15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqdly_pass[0]=15, finish count=1
dqs_perbyte_dly.last_dqdly_pass[1]=15, finish count=2
byte:0, (DQS,DQ)=(8,8)
byte:1, (DQS,DQ)=(8,8)
DRAMC_DQODLY1[200]=88888888
DRAMC_DQODLY2[204]=88888888
20,data:88
[EMI] DRAMC calibration passed
===================================================================
MT7621 stage1 code done
CPU=500000000 HZ BUS=125000000 HZ
===================================================================
U-Boot 1.1.3 (Jul 28 2023 - 15:17:31)
Board: Ralink APSoC DRAM: 64 MB
relocate_code Pointer at: 83fb8000
Config XHCI 40M PLL
******************************
Software System Reset Occurred
******************************
flash manufacture id: 20, device id 40 17
Warning: un-recognized chip ID, please update bootloader!
*** Warning - bad CRC, using default environment
===========================TL-WPA8631Pv3 PERSET GPIO init in uboot=========================
read register GPIO_MODE(0xbe000060), value = 0x0004d52c
set register GPIO_MODE(0xbe000060), value = 0x0004d52c
read register GPIO_CTRL_0(0xbe000600), value = 0x35c00000
set register GPIO_CTRL_0(0xbe000600), value = 0x35c80000
read register GPIO_DATA_0(0xbe000620), value = 0xc83de81e
set register GPIO_DATA_0(0xbe000620), value = 0xc835e81e
=========================TL-WPA8631Pv3 PERSET GPIO init in uboot done==========================
============================================
Ralink UBoot Version: 4.3.0.0
--------------------------------------------
ASIC MT7621A DualCore (MAC to MT7530 Mode)
DRAM_CONF_FROM: Auto-Detection
DRAM_TYPE: DDR2
DRAM bus: 16 bit
Xtal Mode=3 OCP Ratio=1/4
Flash component: SPI Flash
Date:Jul 28 2023 Time:15:17:31
============================================
icache: sets:256, ways:4, linesz:32 ,total:32768
dcache: sets:256, ways:4, linesz:32 ,total:32768
##### The CPU freq = 880 MHZ ####
estimate memory size =64 Mbytes
#Reset_MT7530
=========TL-WPA8631Pv3 GPIO init in uboot=========
RALINK_PIO_BASE(0xbe000600) Reg: 0x4852c
RALINK_PIO_BASE + 4(0xbe000604) Reg: 0x0
RALINK_GPIOMODE_REG(0xbe000060) Reg: 0x4852c
=========TL-WPA8631Pv3 GPIO init in uboot done=========
Please choose the operation:
1: Load system code to SDRAM via TFTP.
2: Load system code then write to Flash via TFTP.
3: Boot system code via Flash (default).
4: Entr boot command line interface.
7: Load Boot Loader code then write to Flash via Serial.
9: Load Boot Loader code then write to Flash via TFTP.
You choosed 4
0
4: System Enter Boot Command Line Interface.
U-Boot 1.1.3 (Jul 28 2023 - 15:17:31)
MT7621 #
Any advice of how to get those bloody things running again would be greatly appreciated.
My Last resort would be getting a full image of the Flash Memory and overwriting it with a working image of another device.... (got all the necessary Hard-/Software for that) but i prefer a Non-Desoldering Solution before using those measures...
Thanks in advance