Build do not boot. - LZMA ERROR 1 [SOLVED]

Hi

I compiled my custom board, but it doesn't boot.
LZMA ERROR 1

What can it be ?
Something in "Teghet image" menù ?
Any offset in the DTS or .MK ? I am starting from that of an INet router

define Device/glinet_gl-mt1300
  $(Device/dsa-migration)
  IMAGE_SIZE := 32448k
  DEVICE_VENDOR := GL.iNet
  DEVICE_MODEL := GL-MT1300
  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware kmod-usb3
endef
TARGET_DEVICES += glinet_gl-mt1300

define Device/geva_batteryPoE-at3-bt
  $(Device/dsa-migration)
  IMAGE_SIZE := 32448k
  DEVICE_VENDOR := GEVA
  DEVICE_MODEL := BatteryPoE_bt
  DEVICE_PACKAGES := kmod-mt76x0e kmod-usb2 kmod-usb-ohci \
	kmod-usb-ledtrig-usbport kmod-usb-storage swconfig iperf3 luci \
	kmod-mt76x0u  kmod-usb-storage-extras kmod-usb-storage-uas \
	chat ppp ppp-mod-pppoa ppp-mod-pppoe ppp-mod-pppol2tp \
	ppp-mod-pptp usb-modeswitch usbutils luci-theme-material \
	block-mount kmod-fs-msdos
endef
TARGET_DEVICES += geva_batteryPoE-at3-bt

define Device/geva_batteryPoE_bt
  SOC := mt7620a
  IMAGE_SIZE := 16064k
  DEVICE_VENDOR := GEVA
  DEVICE_MODEL := BatteryPoE
  DEVICE_PACKAGES := kmod-mt76x0e kmod-usb2 kmod-usb-ohci \
	kmod-usb-ledtrig-usbport kmod-usb-storage swconfig iperf3 luci \
	kmod-mt76x0u  kmod-usb-storage-extras kmod-usb-storage-uas \
	chat ppp ppp-mod-pppoa ppp-mod-pppoe ppp-mod-pppol2tp \
	ppp-mod-pptp usb-modeswitch usbutils luci-theme-material \
	block-mount kmod-fs-msdos
  SUPPORTED_DEVICES += BatteryPoE
endef
TARGET_DEVICES += geva_batteryPoE


===================================================================
                MT7621   stage1 code Mar 12 2015 14:43:30 (ASIC)
                CPU=500000000 HZ BUS=166666666 HZ
==================================================================
Change MPLL source from XTAL to CR...
do MEMPLL setting..
MEMPLL Config : 0x31100000
3PLL mode + External loopback
=== XTAL-40Mhz === DDR-800Mhz ===
PLL4 FB_DL: 0x0, 1/0 = 562/462 01000000
PLL3 FB_DL: 0x6, 1/0 = 532/492 19000000
PLL2 FB_DL: 0x1c, 1/0 = 548/476 71000000
do DDR setting..[01F40000]
Apply DDR3 Setting...(use customer AC)
          0    8   16   24   32   40   48   56   64   72   80   88   96  104  112  120
      --------------------------------------------------------------------------------
0000:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0001:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0002:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0003:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0004:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0005:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0006:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0007:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0008:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0009:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000A:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000B:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000C:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000D:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000E:|    0    0    0    0    0    0    0    0    0    0    0    0    0    1    1    1
000F:|    0    0    0    0    0    1    1    1    1    1    1    1    1    1    1    1
0010:|    1    1    1    1    1    1    1    1    1    1    1    1    1    1    0    0
0011:|    1    1    1    1    1    0    0    0    0    0    0    0    0    0    0    0
0012:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0013:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0014:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0015:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0016:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0017:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0018:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0019:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001A:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001B:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001C:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001D:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001E:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001F:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
DRAMC_DQSCTL1[0e0]=14000000
DRAMC_DQSGCTL[124]=80000000
rank 0 coarse = 16
rank 0 fine = 56
B:|    0    0    0    0    0    0    0    0    1    1    1    0    0    0    0    0
opt_dle value:9
DRAMC_DDR2CTL[07c]=C287221D
DRAMC_PADCTL4[0e4]=000022B3
DRAMC_DQIDLY1[210]=070A0307
DRAMC_DQIDLY2[214]=04090507
DRAMC_DQIDLY3[218]=05060706
DRAMC_DQIDLY4[21c]=03040603
DRAMC_R0DELDLY[018]=0000302F
==================================================================
                RX      DQS perbit delay software calibration
==================================================================
1.0-15 bit dq delay value
==================================================================
bit|     0  1  2  3  4  5  6  7  8  9
--------------------------------------
0 |    7 3 5 6 7 3 8 3 3 3
10 |    6 2 1 4 2 0
--------------------------------------

==================================================================
2.dqs window
x=pass dqs delay value (min~max)center
y=0-7bit DQ of every group
input delay:DQS0 =47 DQS1 = 48
==================================================================
bit     DQS0     bit      DQS1
0  (1~94)47  8  (1~90)45
1  (1~94)47  9  (1~88)44
2  (0~85)42  10  (2~94)48
3  (1~91)46  11  (1~89)45
4  (1~93)47  12  (1~92)46
5  (1~89)45  13  (1~91)46
6  (1~92)46  14  (1~91)46
7  (1~92)46  15  (1~89)45
==================================================================
3.dq delay value last
==================================================================
bit|    0  1  2  3  4  5  6  7  8   9
--------------------------------------
0 |    7 3 10 7 7 5 9 4 6 7
10 |    6 5 3 6 4 3
==================================================================
==================================================================
     TX  perbyte calibration
==================================================================
DQS loop = 15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqsdly_pass[0]=15,  finish count=1
dqs_perbyte_dly.last_dqsdly_pass[1]=15,  finish count=2
DQ loop=15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqdly_pass[0]=15,  finish count=1
dqs_perbyte_dly.last_dqdly_pass[1]=15,  finish count=2
byte:0, (DQS,DQ)=(8,8)
byte:1, (DQS,DQ)=(8,8)
DRAMC_DQODLY1[200]=88888888
DRAMC_DQODLY2[204]=88888888
20,data:88
[EMI] DRAMC calibration passed

===================================================================
                MT7621   stage1 code done
                CPU=500000000 HZ BUS=166666666 HZ
===================================================================


U-Boot 1.1.3 (Aug  9 2022 - 15:15:08)

Board: MediaTek APSoC DRAM: 128 MB

Config XHCI 40M PLL
MediaTek SPI flash driver, SPI clock: 44MHz
spi device id: ef 40 18 0
find flash: W25Q128FV
*** Warning - bad CRC, using default environment

============================================
MediaTek U-Boot Version: 5.0.1.0-6
--------------------------------------------
ASIC MT7621A DualCore (MAC to MT7530 Mode)
DRAM_CONF_FROM: Auto-Detection
DRAM_TYPE: DDR3
DRAM bus: 16 bit
Xtal Mode=3 OCP Ratio=1/3
Flash component: SPI Flash
Date:Aug  9 2022  Time:15:15:08
============================================
icache: sets:256, ways:4, linesz:32, total:32768
dcache: sets:256, ways:4, linesz:32, total:32768

 #### The CPU freq = 880 MHZ ####
 estimate memory size = 128 Mbytes

 Reset MT7530
set LAN/WAN WLLLL

Please choose the operation:
   1: Load system code to SDRAM via TFTP.
   2: Load system code then write to Flash via TFTP.
   3: Boot system code via Flash (default).
   4: Enter boot command line interface.
   5: Load system code then write to Flash via USB Storage.
   9: Load U-Boot code then write to Flash via TFTP.
 0


3: System Boot system code via Flash.
## Checking image at bc050000 ...
   Image Name:   MIPS OpenWrt Linux-5.10.134
   Image Type:   MIPS Linux Kernel Image (lzma compressed)
   Data Size:    2739685 Bytes =  2.6 MB
   Load Address: 80001000
   Entry Point:  80001000
   Verifying Checksum ... OK
   Uncompressing Kernel Image ... LZMA ERROR 1 - must RESET board to recover

===================================================================
                MT7621   stage1 code Mar 12 2015 14:43:30 (ASIC)
                CPU=500000000 HZ BUS=166666666 HZ
==================================================================

From uboot command line load the kernel image into ram manually and then crc test it with the uboot test routine.

I think you will find the image on the flash is incomplete or corrupt. 2.6meg seems small for a 5.10 kernel

need tftp server ? Or slave ?

This is wrinting process of file
openwrt-ramips-mt7621-geva_BatteryPoE-at3-bt-squashfs-sysupgrade.bin
5,75 MB (6.030.423 byte)

 0


3: System Boot system code via Flash.
RESET button pressed!

## Enter to Rescue Mode (manual) ##
(Re)start USB...
USB0:   mtk-xhci: init hccr be1c0000 and hcor be1c0020 hc_length 32
Register 300010f NbrPorts 3
Starting the controller
USB XHCI 0.96
scanning bus 0 for devices... 2 USB Device(s) found
       scanning bus for storage devices... 0 Storage Device(s) found

 No USB Storage found. Upgrade FW failed!

 NetTxPacket = 0x87FB4CC0

 KSEG1ADDR(NetTxPacket) = 0xA7FB4CC0

 NetLoopHttpd,call eth_halt !
Trying eth2

 ETH_STATE_ACTIVE!!
HTTP server is starting at IP: 192.168.1.69
HTTP server is ready!

Request for: /
Request for: /style.css
Data will be downloaded at 0x80200000 in RAM
Upgrade type: firmware
Upload file size: 6030423 bytes
Loading: #######################################
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         #

HTTP upload is done! Upgrading...


****************************
*    FIRMWARE UPGRADING    *
* DO NOT POWER OFF DEVICE! *
****************************

............................................................................................
............................................................................................
.
.
Done!
HTTP ugrade is done! Rebooting...


===================================================================
                MT7621   stage1 code Mar 12 2015 14:43:30 (ASIC)
                CPU=500000000 HZ BUS=166666666 HZ
==================================================================
Change MPLL source from XTAL to CR...
do MEMPLL setting..
MEMPLL Config : 0x31100000
3PLL mode + External loopback
=== XTAL-40Mhz === DDR-800Mhz ===
PLL4 FB_DL: 0x0, 1/0 = 896/128 01000000
PLL3 FB_DL: 0x2, 1/0 = 608/416 09000000
PLL2 FB_DL: 0x1c, 1/0 = 633/391 71000000
do DDR setting..[01F40000]
Apply DDR3 Setting...(use customer AC)
          0    8   16   24   32   40   48   56   64   72   80   88   96  104  112  120
      --------------------------------------------------------------------------------
0000:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0001:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0002:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0003:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0004:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0005:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0006:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0007:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0008:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0009:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000A:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000B:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000C:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000D:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000E:|    0    0    0    0    0    0    0    0    0    0    0    0    0    1    1    1
000F:|    0    0    0    0    0    1    1    1    1    1    1    1    1    1    1    1
0010:|    1    1    1    1    1    1    1    1    1    1    1    1    1    0    0    0
0011:|    1    1    1    1    1    0    0    0    0    0    0    0    0    0    0    0
0012:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0013:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0014:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0015:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0016:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0017:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0018:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0019:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001A:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001B:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001C:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001D:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001E:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001F:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
DRAMC_DQSCTL1[0e0]=14000000
DRAMC_DQSGCTL[124]=80000000
rank 0 coarse = 16
rank 0 fine = 48
B:|    0    0    0    0    0    0    0    0    0    1    1    1    0    0    0    0
opt_dle value:10
DRAMC_DDR2CTL[07c]=C287222D
DRAMC_PADCTL4[0e4]=000022B3
DRAMC_DQIDLY1[210]=080A0408
DRAMC_DQIDLY2[214]=06090809
DRAMC_DQIDLY3[218]=05060506
DRAMC_DQIDLY4[21c]=03030602
DRAMC_R0DELDLY[018]=00002D2D
==================================================================
                RX      DQS perbit delay software calibration
==================================================================
1.0-15 bit dq delay value
==================================================================
bit|     0  1  2  3  4  5  6  7  8  9
--------------------------------------
0 |    8 4 7 8 9 6 9 6 5 4
10 |    6 3 2 5 3 1
--------------------------------------

==================================================================
2.dqs window
x=pass dqs delay value (min~max)center
y=0-7bit DQ of every group
input delay:DQS0 =45 DQS1 = 45
==================================================================
bit     DQS0     bit      DQS1
0  (1~90)45  8  (1~87)44
1  (1~90)45  9  (2~86)44
2  (1~84)42  10  (1~90)45
3  (1~89)45  11  (1~86)43
4  (1~90)45  12  (1~89)45
5  (1~86)43  13  (1~88)44
6  (1~90)45  14  (1~89)45
7  (1~90)45  15  (1~86)43
==================================================================
3.dq delay value last
==================================================================
bit|    0  1  2  3  4  5  6  7  8   9
--------------------------------------
0 |    8 4 10 8 9 8 9 6 6 5
10 |    6 5 2 6 3 3
==================================================================
==================================================================
     TX  perbyte calibration
==================================================================
DQS loop = 15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqsdly_pass[0]=15,  finish count=1
dqs_perbyte_dly.last_dqsdly_pass[1]=15,  finish count=2
DQ loop=15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqdly_pass[0]=15,  finish count=1
dqs_perbyte_dly.last_dqdly_pass[1]=15,  finish count=2
byte:0, (DQS,DQ)=(8,8)
byte:1, (DQS,DQ)=(8,8)
DRAMC_DQODLY1[200]=88888888
DRAMC_DQODLY2[204]=88888888
20,data:88
[EMI] DRAMC calibration passed

===================================================================
                MT7621   stage1 code done
                CPU=500000000 HZ BUS=166666666 HZ
===================================================================


U-Boot 1.1.3 (Aug  9 2022 - 15:15:08)

Board: MediaTek APSoC DRAM: 128 MB

Config XHCI 40M PLL
******************************
Software System Reset Occurred
******************************
MediaTek SPI flash driver, SPI clock: 44MHz
spi device id: ef 40 18 0
find flash: W25Q128FV
*** Warning - bad CRC, using default environment

============================================
MediaTek U-Boot Version: 5.0.1.0-6
--------------------------------------------
ASIC MT7621A DualCore (MAC to MT7530 Mode)
DRAM_CONF_FROM: Auto-Detection
DRAM_TYPE: DDR3
DRAM bus: 16 bit
Xtal Mode=3 OCP Ratio=1/3
Flash component: SPI Flash
Date:Aug  9 2022  Time:15:15:08
============================================
icache: sets:256, ways:4, linesz:32, total:32768
dcache: sets:256, ways:4, linesz:32, total:32768

 #### The CPU freq = 880 MHZ ####
 estimate memory size = 128 Mbytes

 Reset MT7530
set LAN/WAN WLLLL

Please choose the operation:
   1: Load system code to SDRAM via TFTP.
   2: Load system code then write to Flash via TFTP.
   3: Boot system code via Flash (default).
   4: Enter boot command line interface.
   5: Load system code then write to Flash via USB Storage.
   9: Load U-Boot code then write to Flash via TFTP.
 0


3: System Boot system code via Flash.
## Checking image at bc050000 ...
   Image Name:   MIPS OpenWrt Linux-5.10.134
   Image Type:   MIPS Linux Kernel Image (lzma compressed)
   Data Size:    2739685 Bytes =  2.6 MB
   Load Address: 80001000
   Entry Point:  80001000
   Verifying Checksum ... OK
   Uncompressing Kernel Image ... LZMA ERROR 1 - must RESET board to recover

===================================================================
                MT7621   stage1 code Mar 12 2015 14:43:30 (ASIC)
                CPU=500000000 HZ BUS=166666666 HZ
==================================================================
Change MPLL source from XTAL to CR...
do MEMPLL setting..
MEMPLL Config : 0x31100000
3PLL mode + External loopback
=== XTAL-40Mhz === DDR-800Mhz ===
PLL3 FB_DL: 0x0, 1/0 = 528/496 01000000
PLL4 FB_DL: 0x0, 1/0 = 946/78 01000000
PLL2 FB_DL: 0x1b, 1/0 = 558/466 6D000000
do DDR setting..[01F40000]
Apply DDR3 Setting...(use customer AC)
          0    8   16   24   32   40   48   56   64   72   80   88   96  104  112  120
      --------------------------------------------------------------------------------
0000:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0001:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0002:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0003:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0004:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0005:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0006:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0007:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0008:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0009:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000A:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000B:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000C:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000D:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000E:|    0    0    0    0    0    0    0    0    0    0    0    0    0    1    1    1
000F:|    0    0    0    0    0    1    1    1    1    1    1    1    1    1    1    1
0010:|    1    1    1    1    1    1    1    1    1    1    1    1    1    0    0    0
0011:|    1    1    1    1    1    0    0    0    0    0    0    0    0    0    0    0
0012:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0013:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0014:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0015:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0016:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0017:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0018:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0019:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001A:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001B:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001C:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001D:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001E:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001F:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
DRAMC_DQSCTL1[0e0]=14000000
DRAMC_DQSGCTL[124]=80000000
rank 0 coarse = 16
rank 0 fine = 48
B:|    0    0    0    0    0    0    0    0    1    1    1    0    0    0    0    0
opt_dle value:9
DRAMC_DDR2CTL[07c]=C287221D
DRAMC_PADCTL4[0e4]=000022B3
DRAMC_DQIDLY1[210]=0A0A0408
DRAMC_DQIDLY2[214]=05090809
DRAMC_DQIDLY3[218]=05060605
DRAMC_DQIDLY4[21c]=03030602
DRAMC_R0DELDLY[018]=00002D2D
==================================================================
                RX      DQS perbit delay software calibration
==================================================================
1.0-15 bit dq delay value
==================================================================
bit|     0  1  2  3  4  5  6  7  8  9
--------------------------------------
0 |    8 4 7 8 8 6 9 5 5 4
10 |    6 4 2 5 3 1
--------------------------------------

==================================================================
2.dqs window
x=pass dqs delay value (min~max)center
y=0-7bit DQ of every group
input delay:DQS0 =45 DQS1 = 45
==================================================================
bit     DQS0     bit      DQS1
0  (1~90)45  8  (2~88)45
1  (1~90)45  9  (1~86)43
2  (1~84)42  10  (1~90)45
3  (1~86)43  11  (1~87)44
4  (0~88)44  12  (1~89)45
5  (1~86)43  13  (1~88)44
6  (1~90)45  14  (1~89)45
7  (1~90)45  15  (1~86)43
==================================================================
3.dq delay value last
==================================================================
bit|    0  1  2  3  4  5  6  7  8   9
--------------------------------------
0 |    8 4 10 10 9 8 9 5 5 6
10 |    6 5 2 6 3 3
==================================================================
==================================================================
     TX  perbyte calibration
==================================================================
DQS loop = 15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqsdly_pass[0]=15,  finish count=1
dqs_perbyte_dly.last_dqsdly_pass[1]=15,  finish count=2
DQ loop=15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqdly_pass[0]=15,  finish count=1
dqs_perbyte_dly.last_dqdly_pass[1]=15,  finish count=2
byte:0, (DQS,DQ)=(8,8)
byte:1, (DQS,DQ)=(8,8)
DRAMC_DQODLY1[200]=88888888
DRAMC_DQODLY2[204]=88888888
20,data:88
[EMI] DRAMC calibration passed

===================================================================
                MT7621   stage1 code done
                CPU=500000000 HZ BUS=166666666 HZ
===================================================================


U-Boot 1.1.3 (Aug  9 2022 - 15:15:08)

Board: MediaTek APSoC DRAM: 128 MB

Config XHCI 40M PLL
******************************
Software System Reset Occurred
******************************
MediaTek SPI flash driver, SPI clock: 44MHz
spi device id: ef 40 18 0
find flash: W25Q128FV
*** Warning - bad CRC, using default environment

============================================
MediaTek U-Boot Version: 5.0.1.0-6
--------------------------------------------
ASIC MT7621A DualCore (MAC to MT7530 Mode)
DRAM_CONF_FROM: Auto-Detection
DRAM_TYPE: DDR3
DRAM bus: 16 bit
Xtal Mode=3 OCP Ratio=1/3
Flash component: SPI Flash
Date:Aug  9 2022  Time:15:15:08
============================================
icache: sets:256, ways:4, linesz:32, total:32768
dcache: sets:256, ways:4, linesz:32, total:32768

 #### The CPU freq = 880 MHZ ####
 estimate memory size = 128 Mbytes

 Reset MT7530
set LAN/WAN WLLLL

Please choose the operation:
   1: Load system code to SDRAM via TFTP.
   2: Load system code then write to Flash via TFTP.
   3: Boot system code via Flash (default).
   4: Enter boot command line interface.
   5: Load system code then write to Flash via USB Storage.
   9: Load U-Boot code then write to Flash via TFTP.
 0


3: System Boot system code via Flash.
## Checking image at bc050000 ...
   Image Name:   MIPS OpenWrt Linux-5.10.134
   Image Type:   MIPS Linux Kernel Image (lzma compressed)
   Data Size:    2739685 Bytes =  2.6 MB
   Load Address: 80001000
   Entry Point:  80001000
   Verifying Checksum ... OK
   Uncompressing Kernel Image ... LZMA ERROR 1 - must RESET board to recover

===================================================================
                MT7621   stage1 code Mar 12 2015 14:43:30 (ASIC)
                CPU=500000000 HZ BUS=166666666 HZ
==================================================================
Change MPLL source from XTAL to CR...
do MEMPLL setting..
MEMPLL Config : 0x31100000
3PLL mode + External loopback
=== XTAL-40Mhz === DDR-800Mhz ===
PLL4 FB_DL: 0x0, 1/0 = 953/71 01000000
PLL3 FB_DL: 0x3, 1/0 = 636/388 0D000000
PLL2 FB_DL: 0x1b, 1/0 = 515/509 6D000000
do DDR setting..[01F40000]
Apply DDR3 Setting...(use customer AC)
          0    8   16   24   32   40   48   56   64   72   80   88   96  104  112  120
      --------------------------------------------------------------------------------
0000:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0001:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0002:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0003:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0004:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0005:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0006:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0007:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0008:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0009:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000A:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000B:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000C:|    0    0    0    0    0    0    0    0    0    0    0

Please choose the operation:
   1: Load system code to SDRAM via TFTP.
   2: Load system code then write to Flash via TFTP.
   3: Boot system code via Flash (default).
   4: Enter boot command line interface.
   5: Load system code then write to Flash via USB Storage.
   9: Load U-Boot code then write to Flash via TFTP.

You choosed 4

 0


4: System Enter Boot Command Line Interface.

U-Boot 1.1.3 (Aug  9 2022 - 15:15:08)
MT7621 # help
?       - alias for 'help'
bootm   - boot application image from memory
cp      - memory copy
crc32   - checksum calculation
erase   - erase SPI FLASH memory
fatinfo - print information about filesystem
fatload - load binary file from a dos filesystem
fatls   - list files in a directory (default /)
go      - start application at address 'addr'
help    - print online help
httpd   - start web server for firmware recovery
md      - memory display
mdio   - Ralink PHY register R/W command !!
mm      - memory modify (auto-incrementing)
nm      - memory modify (constant address)
printenv- print environment variables
reset   - Perform RESET of the CPU
rf      - read/write rf register
saveenv - save environment variables to persistent storage
setenv  - set environment variables
spi     - spi command
tftpboot- boot image via network using TFTP protocol
tftpd    -load the data by tftp protocol
usb     - USB sub-system
usbboot - boot from USB device
version - print monitor version
MT7621 #

Hmm that’s a very limited uboot command set.

Tftpbooting the kernel is a good starting point, you need a tftp server.

How is your boot command set in the uboot envs? Are you sure you’re loading the full kernel image to ram before booting?

I'm not sure of anything, with the exception of what I showed you.

I load the firmware via html page. (Log show before)

if i type tftpd command, not work.

U-Boot 1.1.3 (Aug  9 2022 - 15:15:08)
MT7621 # help
?       - alias for 'help'
bootm   - boot application image from memory
cp      - memory copy
crc32   - checksum calculation
erase   - erase SPI FLASH memory
fatinfo - print information about filesystem
fatload - load binary file from a dos filesystem
fatls   - list files in a directory (default /)
go      - start application at address 'addr'
help    - print online help
httpd   - start web server for firmware recovery
md      - memory display
mdio   - Ralink PHY register R/W command !!
mm      - memory modify (auto-incrementing)
nm      - memory modify (constant address)
printenv- print environment variables
reset   - Perform RESET of the CPU
rf      - read/write rf register
saveenv - save environment variables to persistent storage
setenv  - set environment variables
spi     - spi command
tftpboot- boot image via network using TFTP protocol
tftpd    -load the data by tftp protocol
usb     - USB sub-system
usbboot - boot from USB device
version - print monitor version
MT7621 # tftpd
## Checking image at 80200000 ...
Bad Magic Number,080020A2

## Enter to Rescue Mode (image error) ##

 NetTxPacket = 0x87FB4CC0

 KSEG1ADDR(NetTxPacket) = 0xA7FB4CC0

 NetLoopHttpd,call eth_halt !
Trying eth2

 ETH_STATE_ACTIVE!!
HTTP server is starting at IP: 192.168.1.69
HTTP server is ready!

To boot via tftp use tftpboot

You may find it useful to do some reading on uboot configuration and tools to keep working with a custom device.

Also, printenv will show all current uboot settings, including the bootcmd, which should show what size image it is trying to load

I renamed
openwrt-ramips-mt7621-geva_BatteryPoE-at3-bt-squashfs-sysupgrade.bin
on
image.trx

Opened SolarWinds TFTP Server at 192.168.1.20

MT7621 # tftpboot
TFTP from server 192.168.1.20; our IP address is 192.168.1.69
Filename 'image.trx'.

Loading: Got ARP REPLY, set server/gtwy eth addr (3c:7c:3f:c3:27:f0)
Got it
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         ########
done
Bytes transferred = 6030423 (5c0457 hex)
LoadAddr=80200000 NetBootFileXferSize=005c0457
MT7621 # crc32
Usage:
crc32   - checksum calculation
MT7621 # crc32   - checksum calculation
CRC32 for 00000000 ... 0000000b ==> b213822e

Ok, so your image is 6mb but your bootcmd loads 2.9mb

You will need to adapt the bootcmd to suit.

For the image loaded from tftpboot you should now be able to run bootm 80200000 and boot the image from ram.

Not, same error

Loading: T Got ARP REPLY, set server/gtwy eth addr (3c:7c:3f:c3:27:f0)
Got it
T
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         ########
done
Bytes transferred = 6030423 (5c0457 hex)
LoadAddr=80200000 NetBootFileXferSize=005c0457
MT7621 # bootm 80200000
## Checking image at 80200000 ...
   Image Name:   MIPS OpenWrt Linux-5.10.134
   Image Type:   MIPS Linux Kernel Image (lzma compressed)
   Data Size:    2739685 Bytes =  2.6 MB
   Load Address: 80001000
   Entry Point:  80001000
   Verifying Checksum ... OK
   Uncompressing Kernel Image ... LZMA ERROR 1 - must RESET board to recover

So in the first case, it means the size of the kernel, and in the second case, the size of the entire firmware.

On the advice of a friend, I am trying to recompile as follows:

define Device/geva_BatteryPoE-at3-bt
  $(Device/dsa-migration)
  $(Device/uimage-lzma-loader)  
  IMAGE_SIZE := 32448k
  DEVICE_VENDOR := GEVA
  DEVICE_MODEL := BatteryPoE-at3-bt
  DEVICE_PACKAGES := kmod-mt76x0e kmod-usb2 kmod-usb-ohci \
	kmod-usb-ledtrig-usbport kmod-usb-storage swconfig iperf3 luci \
	kmod-mt76x0u  kmod-usb-storage-extras kmod-usb-storage-uas \
	chat ppp ppp-mod-pppoa ppp-mod-pppoe ppp-mod-pppol2tp \
	ppp-mod-pptp usb-modeswitch usbutils luci-theme-material \
	block-mount kmod-fs-msdos
endef
TARGET_DEVICES += geva_BatteryPoE-at3-bt

$(Device/uimage-lzma-loader)

SOLVED

kernel started

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