hi
please dont be so negative.
there already a basic support for this soc in u-boot.
there is also a dtsi file and a dtb for gerg board....
so thats something to build on.
that soc is similar to bcm63268 and uses compatibles ...
i am not giving false hope either to any one am not expert or somthing
but what it will take to use same route like 63268 ?
here is dtsi:
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
*/
#include "skeleton.dtsi"
/ {
compatible = "brcm,bcm6838";
cpus {
reg = <0x14e00000 0x4>;
#address-cells = <1>;
#size-cells = <0>;
u-boot,dm-pre-reloc;
cpu@0 {
compatible = "brcm,bcm6838-cpu", "mips,mips4Kc";
device_type = "cpu";
reg = <0>;
u-boot,dm-pre-reloc;
};
cpu@1 {
compatible = "brcm,bcm6838-cpu", "mips,mips4Kc";
device_type = "cpu";
reg = <1>;
u-boot,dm-pre-reloc;
};
};
clocks {
compatible = "simple-bus";
u-boot,dm-pre-reloc;
periph_osc: periph-osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
u-boot,dm-pre-reloc;
};
};
ubus {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
u-boot,dm-pre-reloc;
memory: memory-controller@12000000 {
compatible = "brcm,bcm6328-mc";
reg = <0x12000000 0x1000>;
u-boot,dm-pre-reloc;
};
gpio_test_port: syscon@14e00294 {
compatible = "syscon";
reg = <0x14e00294 0x1c>;
};
pinctrl: pinctrl {
compatible = "brcm,bcm6838-pinctrl";
regmap = <&gpio_test_port>;
brcm,pins-count = <74>;
brcm,functions-count = <8>;
};
uart0: serial@14e00500 {
compatible = "brcm,bcm6345-uart";
reg = <0x14e00500 0x18>;
clocks = <&periph_osc>;
status = "disabled";
};
wdt0: watchdog@14e002d0 {
compatible = "brcm,bcm6345-wdt";
reg = <0x14e002d0 0xc>;
clocks = <&periph_osc>;
};
wdt1: watchdog@14e002dc {
compatible = "brcm,bcm6345-wdt";
reg = <0x14e002dc 0xc>;
clocks = <&periph_osc>;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdt0>;
};
leds: led-controller@14e00f00 {
compatible = "brcm,bcm6328-leds";
reg = <0x14e00f00 0x28>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gpio_lo: gpio-controller@14e00100 {
compatible = "brcm,bcm6345-gpio";
reg = <0x14e00100 0x4>, <0x14e0012c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio_mid0: gpio-controller@14e00104 {
compatible = "brcm,bcm6345-gpio";
reg = <0x14e00104 0x4>, <0x14e00130 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio_mid1: gpio-controller@14e00108 {
compatible = "brcm,bcm6345-gpio";
reg = <0x14e00108 0x4>, <0x14e00134 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
nand: nand-controller@14e02200 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,nand-bcm6838",
"brcm,brcmnand-v5.0",
"brcm,brcmnand";
reg-names = "nand", "nand-int-base", "nand-cache";
reg = <0x14e02200 0x180>,
<0x14e000f0 0x10>,
<0x14e02600 0x180>;
status = "disabled";
};
};
};
then dtb for some board :
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
*/
#include "skeleton.dtsi"
/ {
compatible = "brcm,bcm6838";
cpus {
reg = <0x14e00000 0x4>;
#address-cells = <1>;
#size-cells = <0>;
u-boot,dm-pre-reloc;
cpu@0 {
compatible = "brcm,bcm6838-cpu", "mips,mips4Kc";
device_type = "cpu";
reg = <0>;
u-boot,dm-pre-reloc;
};
cpu@1 {
compatible = "brcm,bcm6838-cpu", "mips,mips4Kc";
device_type = "cpu";
reg = <1>;
u-boot,dm-pre-reloc;
};
};
clocks {
compatible = "simple-bus";
u-boot,dm-pre-reloc;
periph_osc: periph-osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
u-boot,dm-pre-reloc;
};
};
ubus {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
u-boot,dm-pre-reloc;
memory: memory-controller@12000000 {
compatible = "brcm,bcm6328-mc";
reg = <0x12000000 0x1000>;
u-boot,dm-pre-reloc;
};
gpio_test_port: syscon@14e00294 {
compatible = "syscon";
reg = <0x14e00294 0x1c>;
};
pinctrl: pinctrl {
compatible = "brcm,bcm6838-pinctrl";
regmap = <&gpio_test_port>;
brcm,pins-count = <74>;
brcm,functions-count = <8>;
};
uart0: serial@14e00500 {
compatible = "brcm,bcm6345-uart";
reg = <0x14e00500 0x18>;
clocks = <&periph_osc>;
status = "disabled";
};
wdt0: watchdog@14e002d0 {
compatible = "brcm,bcm6345-wdt";
reg = <0x14e002d0 0xc>;
clocks = <&periph_osc>;
};
wdt1: watchdog@14e002dc {
compatible = "brcm,bcm6345-wdt";
reg = <0x14e002dc 0xc>;
clocks = <&periph_osc>;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdt0>;
};
leds: led-controller@14e00f00 {
compatible = "brcm,bcm6328-leds";
reg = <0x14e00f00 0x28>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gpio_lo: gpio-controller@14e00100 {
compatible = "brcm,bcm6345-gpio";
reg = <0x14e00100 0x4>, <0x14e0012c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio_mid0: gpio-controller@14e00104 {
compatible = "brcm,bcm6345-gpio";
reg = <0x14e00104 0x4>, <0x14e00130 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio_mid1: gpio-controller@14e00108 {
compatible = "brcm,bcm6345-gpio";
reg = <0x14e00108 0x4>, <0x14e00134 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
nand: nand-controller@14e02200 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,nand-bcm6838",
"brcm,brcmnand-v5.0",
"brcm,brcmnand";
reg-names = "nand", "nand-int-base", "nand-cache";
reg = <0x14e02200 0x180>,
<0x14e000f0 0x10>,
<0x14e02600 0x180>;
status = "disabled";
};
};
};
even if that soc isnt going mainline or upstream or if it does and needed too much efforts and time to maintain it and no support for pon or wifi
i realy dont see why not make an effort to make them supported if there are peapole willing to make it happen.
personnelly i have lot of devices based on that , more than
20 of arcadyn prv3399 (livebox fibra)alone_with no gpon epon_
then there is zte f680v4
sagem 5655v2 witch have u-boot supported a long time ago_ may be from the work of noltari _ who by the way does great work in bmips and cfe -thanks man!_
rv6699 there is lot of infos in russian site 4pda for this device
askey rtf3505vw
gpt 2541gnac
igat gw040
u-fiber nano g
and others
i see those devices as probable cheap gigabit openflow switchs.