Adding support for XikeStor SKS7300 series

andyboeh · February 27, 2026, 7:57pm

Replying to myself again, since this series doesn't seem to be of much interest except to me:

I was very busy with real life, but I've made some progress:

U-Boot works, rtk network on works for the copper ports. tftpboot is working as well.
U-Boot does not accept a standard image format, it requires an obfuscated image with a specific header.
I've understood enough of the header to write a utility to generate a valid image header! WiP code: https://github.com/andyboeh/firmware-utils/tree/sks7300-img

Now I need to create an obfuscator to finally be able to boot an OpenWrt initramfs image! This shouldn't be too hard, based on the deobfuscator code.

For flashing the firmware, I'm thinking about a strategy similar to the GS1920: The image header will contain either rt-loader or the kernel image, but nothing more. This is necessary since the complete image is CRC-checked and the writable filesystem would render the image invalid.

Edit: Partial success in booting an initramfs image! My obfuscator + image utility is accepted by U-Boot and rt-loader starts. It then halts with LZMA data is corrupt, but that's something!

Edit2: The data isn't corrupt anymore, but I suppose there is a watchdog involved. Even if rt-loader is in an endless loop, the system reboots after a few seconds. On the board, there is an external watchdog chip (SGM706B), but I would be surprised if it was on in U-Boot!? The OEM boot log initializes the watchdog (wdt dev init: gpio=20), so who knows?

Edit3: And it was the watchdog. Upon adding CONFIG_GPIO_WATCHDOG and defining the pin in the DTS (it is pin 20, btw), the kernel is booting up!

@plappermaul Since rt-loader can't trigger the watchdog, there is no chance of using it on this switch, right?

plappermaul · March 1, 2026, 11:20am

we can add all meaningful things to rt-loader that we like. @jonasj added an early prom quirk because of other watchdog issues. See https://github.com/openwrt/openwrt/commit/7f743646724f2f75beb8bcf15ab2e5f0064df555

So what will help you here?

andyboeh · March 1, 2026, 9:47pm

For now, OpenWrt is booting fine without rt-loader. U-Boot supports booting an LZMA compressed kernel, so that should be fine.
Initially, I wanted to convince the bootloader that rt-loader is the complete image so that I don't have to deal with checksums during OpenWrt build (as I did on the ZyXEL GS1920), but this can be handled with the right build recipe. But first, GPIOs and network config.

@jonasj If I'm not mistaken, you've also been working on the TP-Link TL-ST1008Fv2 switch. This device has a GPIO watchdog defined, but the wdt-gpio driver is not enabled in the kernel config. Hence, the watchdog is never activated/triggered.

On this Xikestor, the watchdog is happy if I add

CONFIG_GPIO_WATCHDOG=y
CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y

to the kernel config file. There is no need for any quirk, but then this device uses GPIO20 to feed the watchdog and not the system LED as on your Xikestor.

jonasj · March 1, 2026, 10:14pm

Most of the work for the TP-Link was done by someone else and I just polished and submitted it. Since it worked, I didn't pay any attention to that watchdog. But you are right, this is a dead node in the DTS. This seems to be one of the cases where the U-boot "configures" the watchdog feeding (here by permanently setting the GPIO to HIGH) and since OpenWrt later doesn't change something there, it just works. So it doesn't need to be triggered, it is fine if the GPIO is permanently HIGH. In fact, if I pull the GPIO down with gpioset, the switch is reset.

For my XikeStor, there was no other way instead of that quirk. The watchdog kicks in at a stage where the kernel doesn't even think about loading drivers. It seems that XikeStor itself cannot decide how to use watchdogs because the behavior seems to be different with every device. If the GPIO watchdog helps for the SKS7300, that's the good and correct way.

jonasj · March 2, 2026, 11:34am

@andyboeh A small side track related to zynsig ... do you have any experience with that to be able to flash an image via the web interface? My XS1930 devices work fine but it's a nightmare to go through that serial upload + flash process.

Some attempts to make a combined image (loader + padding + kernel + rootfs) with only rt-loader signed and the whole image signed failed so far.

andyboeh · March 2, 2026, 6:13pm

Yeah, I experimented a bit with that but I gave up after a relatively short time. The zynsig utility only creates the basic checksums/infos that BootExt expects, but I suppose that there are a few other checks in the web interface - for example the partition map. Have a look at mkzynfw.c, that creates an image with partition map and a few other details, but IIRC there are a some important differences.

My initial idea was to recreate the partition map, fake rt-loader (well, back then lzma-loader) as BootExt and OpenWrt as the ROM image. But then is another problem with adding the whole image: The checksum is created over the entire file. As soon as the partition is writable, the checksum doesn't match any longer and BootBase fails to load the image - this would need to be worked around. That's one of the reasons why I decided to only sign rt-loader and bypass the checksum for the rest of the image.

jonasj · March 3, 2026, 9:05am

Thanks, I'll see if I have some success extracting that information somehow out of the Zyxel firmware, or if it's a dead end.

andyboeh · March 7, 2026, 11:15pm

Short update:

RJ45 ports are working (so far only 1G tested)
LEDs are working
all i2c busses are working
temperature sensor is working
boot from flash

Missing:

SFP GPIOs

Investigating:

Fan control

Fan Control: There is a separate GD32E230F8 MCU connected via i2c (address 0x34). Fan Duty can be controlled by writing 4 bytes to address 0x0:

data[0] = 0xfe
data[1] = duty cycle
data[2] = ~duty cycle
data[3] = 0xed

To set fan to 50%, write: 0xfe 0x32 0xcd 0xed
The fan can be set to as low as 10%, but it's not possible to set it to 0%.

The fan control logic is supposedly:

Temp < 50 -> 50%
50 <= Temp < 70 -> 75%
70 <= Temp -> 100%

The fan reports its RPM. Read 2 bytes from 0x03 to get the actual fan speed.

andyboeh · March 14, 2026, 7:39pm

I fear I've hit a roadblock here: I added the SFPs to the DTS and I noticed that two of the four copper ports are now inaccessible while the SFP ports are working properly.
I then flashed the firmware and did a cold boot: all copper ports don't work, SFPs are fine.

I fear that the problem is once again that U-Boot does not initialize the network. And there is no bootcmd on this very special U-Boot that would allow me to initialize the network.

The board uses RTL8261BE PHYs, I'm unsure if they are supported - or is it likely a problem with the PCS driver? @jonasj @plappermaul your input would be much appreciated here!

Here is the boot log - dts in the repo: https://github.com/andyboeh/openwrt/commit/2dd2b793bdc672da5378c79e2619e1d38a8cbefc

[    0.388352] realtek-otto-serdes-mdio 1b000000.switchcore:mdio-serdes: Realtek SerDes mdio bus initialized, 12 SerDes, 64 pages, 32 registers
[    0.389274] realtek-otto-pcs 1b000000.switchcore:pcs: Realtek PCS driver initialized
[    0.390604] Probing RTL838X eth device pdev: 8195ae00, dev: 8195ae10
[    0.393963] i2c_dev: i2c /dev entries driver
[    0.433063] NET: Registered PF_INET6 protocol family
[    0.441349] Segment Routing with IPv6
[    0.441505] In-situ OAM (IOAM) with IPv6
[    0.441683] NET: Registered PF_PACKET protocol family
[    0.442374] 8021q: 802.1Q VLAN Support v1.8
[    0.497197] i2c-gpio i2c_gpio: using lines 522 (SDA) and 521 (SCL)
[    0.498405] sfp sfp-p1: Host maximum power 1.5W
[    0.500036] sfp sfp-p2: Host maximum power 1.5W
[    0.501544] sfp sfp-p3: Host maximum power 1.5W
[    0.503106] sfp sfp-p4: Host maximum power 1.5W
[    0.504598] Probing RTL838X eth device pdev: 8195ae00, dev: 8195ae10
[    0.507212] Using MAC 8c:a6:82:70:e3:84
[    0.518341] rtldsa_93xx_setup called
[    0.518454] In rtldsa_vlan_setup
[    0.518476] rtl83xx-switch switch@1b000000: MC_PMASK_ALL_PORTS: 000000001fffffff
[    1.535628] rtldsa_enable_phy_polling:          f110101
[    1.536026] rtl83xx-switch switch@1b000000: led_set0 has 2 LEDs configured
[    1.536223] rtl83xx-switch switch@1b000000: configuring for fixed/internal link mode
[    1.544646] Realtek RTL8261N realtek-mdio:18: rtkphy_config_init:80 [RTL8261N/RTL8264/RTL826XB] phy_id: 0x1CCAF3 PHYAD:24
[    1.544885] rtl83xx-switch switch@1b000000 lan8 (uninitialized): PHY [realtek-mdio:18] driver [Realtek RTL8261N] (irq=POLL)
[    1.547405] Realtek RTL8261N realtek-mdio:19: rtkphy_config_init:80 [RTL8261N/RTL8264/RTL826XB] phy_id: 0x1CCAF3 PHYAD:25
[    1.547947] rtl83xx-switch switch@1b000000 lan7 (uninitialized): PHY [realtek-mdio:19] driver [Realtek RTL8261N] (irq=POLL)
[    1.550884] Realtek RTL8261N realtek-mdio:1a: rtkphy_config_init:80 [RTL8261N/RTL8264/RTL826XB] phy_id: 0x1CCAF3 PHYAD:26
[    1.551424] rtl83xx-switch switch@1b000000 lan6 (uninitialized): PHY [realtek-mdio:1a] driver [Realtek RTL8261N] (irq=POLL)
[    1.554249] Realtek RTL8261N realtek-mdio:1b: rtkphy_config_init:80 [RTL8261N/RTL8264/RTL826XB] phy_id: 0x1CCAF3 PHYAD:27
[    1.554692] rtl83xx-switch switch@1b000000 lan5 (uninitialized): PHY [realtek-mdio:1b] driver [Realtek RTL8261N] (irq=POLL)
[    1.558051] rtl838x-eth 1b000000.switchcore:ethernet eth0: entered promiscuous mode
[    1.558307] DSA: tree 0 setup
[    1.558490] LINK state irq: 23
[    1.558842] rtl930x_dbgfs_init called
[    1.560527] rtl83xx-switch switch@1b000000: Link is Up - 10Gbps/Full - flow control off
[    1.562801] clk: Disabling unused clocks
[    1.572094] VFS: Mounted root (squashfs filesystem) readonly on device 31:6.
[    1.577934] Freeing unused kernel image (initmem) memory: 1272K
[    1.577981] This architecture does not have kernel memory protection.
[    1.578003] Run /sbin/init as init process
[    1.578012]   with arguments:
[    1.578019]     /sbin/init
[    1.578027]   with environment:
[    1.578034]     HOME=/
[    1.578042]     TERM=linux
[    2.177959] init: Console is alive
[    2.178529] init: - watchdog -
[    2.541168] kmodloader: loading kernel modules from /etc/modules-boot.d/*
[    2.589013] gpio_button_hotplug: loading out-of-tree module taints kernel.
[    2.594156] kmodloader: done loading kernel modules from /etc/modules-boot.d/*
[    2.599148] init: - preinit -
[    7.355669] random: crng init done
[    8.166086] RESETTING CPU_PORT 28
[    8.365706] rtl838x-eth 1b000000.switchcore:ethernet eth0: configuring for fixed/internal link mode
[    8.365754] In rteth_mac_config, mode 1
[    8.366833] rtl83xx-switch switch@1b000000 lan1: configuring for inband/1000base-x link mode
[    8.366889] realtek-otto-pcs 1b000000.switchcore:pcs: configure SerDes 2 for mode 1000base-x
[    8.377254] rtpcs_930x_phy_enable_10g_1g 1gbit phy: 00001140
[    8.377300] rtpcs_930x_phy_enable_10g_1g 1gbit phy enabled: 00001140
[    8.377317] rtpcs_930x_phy_enable_10g_1g 10gbit phy: 00002040
[    8.377332] rtpcs_930x_phy_enable_10g_1g 10gbit phy after: 00002040
[    8.377348] rtpcs_930x_phy_enable_10g_1g set medium: 00000000
[    8.377363] rtpcs_930x_phy_enable_10g_1g set medium after: 00000002
[    8.377375] rtpcs_930x_setup_serdes: Configuring RTL9300 SERDES 2
[    8.377444] rtpcs_930x_sds_config_pll: SDS 2 using ring PLL for mode 2
[    8.377624] rtl838x-eth 1b000000.switchcore:ethernet eth0: Link is Up - 1Gbps/Full - flow control off
[    8.426207] rtpcs_930x_sds_10g_idle WARNING: Waiting for RX idle timed out, SDS 2
[    8.426249] start_1.1.1 initial value for sds 2
[    8.426321] end_1.1.1 --
[    8.426331] start_1.1.2 Load DFE init. value
[    8.426343] end_1.1.2
[    8.426351] start_1.1.3 disable LEQ training,enable DFE clock
[    8.426374] end_1.1.3 --
[    8.426383] start_1.1.4 offset cali setting
[    8.426395] end_1.1.4
[    8.426403] start_1.1.5 LEQ and DFE setting
[    8.426433] end_1.1.5
[    8.431439] start_1.2.1 ForegroundOffsetCal_Manual
[    8.431456] end_1.2.1
[    8.436536] start_1.2.3 Foreground Calibration
[    8.436589] rtpcs_930x_sds_do_rx_calibration_2_3: fgcal_gray: 31, fgcal_binary 31
[    8.436614] rtpcs_930x_sds_do_rx_calibration_2_3: end_1.2.3
[    8.436625] start_1.4.1
[    8.657290] end_1.4.1
[    8.657321] start_1.4.2
[    8.658354] vth_set_bin = 7
[    8.658369] vth_set_bin = 3
[    8.658381] Vth Maunal = 0
[    8.759725] Tap0 Sign : +
[    8.759756] tap0_coef_bin = 31
[    8.759772] tap0 manual = 0
[    8.759792] end_1.4.2
[    8.831330] 8021q: adding VLAN 0 to HW filter on device lan1
[   13.364837] jffs2: notice: (636) jffs2_build_xattr_subsystem: complete building xattr subsystem, 7 of xdatum (0 unchecked, 1 orphan) and 8 of xref (1 dead, 0 orphan) found.
[   13.367695] mount_root: switching to jffs2 overlay
[   13.372267] overlayfs: upper fs does not support tmpfile.
[   13.380332] urandom-seed: Seeding with /etc/urandom.seed
[   13.487770] procd: - early -
[   13.488192] procd: - watchdog -
[   14.160790] procd: - watchdog -
[   14.162110] procd: - ubus -
[   14.337420] procd: - init -
[   15.323651] kmodloader: loading kernel modules from /etc/modules.d/*
[   15.403933] lm75 4-0048: hwmon1: sensor 'lm75'
[   15.507873] kmodloader: done loading kernel modules from /etc/modules.d/*
[   16.804848] urngd: v1.0.2 started.
[   24.240639] in rteth_stop
[   24.240859] rtl838x-eth 1b000000.switchcore:ethernet eth0: Link is Down
[   24.823419] RESETTING CPU_PORT 28
[   25.023038] rtl838x-eth 1b000000.switchcore:ethernet eth0: configuring for fixed/internal link mode
[   25.023086] In rteth_mac_config, mode 1
[   25.023676] rtl838x-eth 1b000000.switchcore:ethernet eth0: Link is Up - 1Gbps/Full - flow control off
[   25.030038] rtl83xx-switch switch@1b000000 lan1: configuring for inband/sgmii link mode
[   25.030091] realtek-otto-pcs 1b000000.switchcore:pcs: configure SerDes 2 for mode sgmii
[   25.041389] rtpcs_930x_phy_enable_10g_1g 1gbit phy: 00001140
[   25.041486] rtpcs_930x_phy_enable_10g_1g 1gbit phy enabled: 00001140
[   25.041538] rtpcs_930x_phy_enable_10g_1g 10gbit phy: 00002040
[   25.041572] rtpcs_930x_phy_enable_10g_1g 10gbit phy after: 00002040
[   25.041608] rtpcs_930x_phy_enable_10g_1g set medium: 00000002
[   25.041645] rtpcs_930x_phy_enable_10g_1g set medium after: 00000002
[   25.041669] rtpcs_930x_setup_serdes: Configuring RTL9300 SERDES 2
[   25.041775] rtpcs_930x_sds_config_pll: SDS 2 using ring PLL for mode 5
[   25.101284] rtpcs_930x_sds_10g_idle WARNING: Waiting for RX idle timed out, SDS 2
[   25.101330] start_1.1.1 initial value for sds 2
[   25.101403] end_1.1.1 --
[   25.101413] start_1.1.2 Load DFE init. value
[   25.101425] end_1.1.2
[   25.101434] start_1.1.3 disable LEQ training,enable DFE clock
[   25.101457] end_1.1.3 --
[   25.101466] start_1.1.4 offset cali setting
[   25.101478] end_1.1.4
[   25.101486] start_1.1.5 LEQ and DFE setting
[   25.101513] end_1.1.5
[   25.106920] start_1.2.1 ForegroundOffsetCal_Manual
[   25.106972] end_1.2.1
[   25.112929] start_1.2.3 Foreground Calibration
[   25.113033] rtpcs_930x_sds_do_rx_calibration_2_3: fgcal_gray: 31, fgcal_binary 31
[   25.113089] rtpcs_930x_sds_do_rx_calibration_2_3: end_1.2.3
[   25.113115] start_1.4.1
[   25.378814] end_1.4.1
[   25.378864] start_1.4.2
[   25.380139] vth_set_bin = 7
[   25.380186] vth_set_bin = 3
[   25.380204] Vth Maunal = 0
[   25.482370] Tap0 Sign : +
[   25.482405] tap0_coef_bin = 31
[   25.482423] tap0 manual = 0
[   25.482443] end_1.4.2
[   25.554243] 8021q: adding VLAN 0 to HW filter on device lan1
[   25.555969] switch: port 1(lan1) entered blocking state
[   25.556036] switch: port 1(lan1) entered disabled state
[   25.556131] rtl83xx-switch switch@1b000000 lan1: entered allmulticast mode
[   25.556175] rtl838x-eth 1b000000.switchcore:ethernet eth0: entered allmulticast mode
[   25.556984] rtl83xx-switch switch@1b000000 lan1: entered promiscuous mode
[   25.621513] rtl83xx-switch switch@1b000000 lan2: configuring for inband/sgmii link mode
[   25.621589] realtek-otto-pcs 1b000000.switchcore:pcs: configure SerDes 3 for mode sgmii
[   25.633762] rtpcs_930x_phy_enable_10g_1g 1gbit phy: 00001140
[   25.633835] rtpcs_930x_phy_enable_10g_1g 1gbit phy enabled: 00001140
[   25.633860] rtpcs_930x_phy_enable_10g_1g 10gbit phy: 00002040
[   25.633883] rtpcs_930x_phy_enable_10g_1g 10gbit phy after: 00002040
[   25.633907] rtpcs_930x_phy_enable_10g_1g set medium: 00000000
[   25.633930] rtpcs_930x_phy_enable_10g_1g set medium after: 00000002
[   25.633949] rtpcs_930x_setup_serdes: Configuring RTL9300 SERDES 3
[   25.634018] rtpcs_930x_sds_config_pll: SDS 3 using ring PLL for mode 5
[   25.688841] rtpcs_930x_sds_10g_idle WARNING: Waiting for RX idle timed out, SDS 3
[   25.688938] start_1.1.1 initial value for sds 3
[   25.689080] end_1.1.1 --
[   25.689117] start_1.1.2 Load DFE init. value
[   25.689138] end_1.1.2
[   25.689154] start_1.1.3 disable LEQ training,enable DFE clock
[   25.689190] end_1.1.3 --
[   25.689208] start_1.1.4 offset cali setting
[   25.689230] end_1.1.4
[   25.689244] start_1.1.5 LEQ and DFE setting
[   25.689293] end_1.1.5
[   25.695254] start_1.2.1 ForegroundOffsetCal_Manual
[   25.695322] end_1.2.1
[   25.701600] start_1.2.3 Foreground Calibration
[   25.701691] rtpcs_930x_sds_do_rx_calibration_2_3: fgcal_gray: 31, fgcal_binary 31
[   25.701744] rtpcs_930x_sds_do_rx_calibration_2_3: end_1.2.3
[   25.701770] start_1.4.1
[   25.965317] end_1.4.1
[   25.965359] start_1.4.2
[   25.966729] vth_set_bin = 7
[   25.966790] vth_set_bin = 3
[   25.966820] Vth Maunal = 0
[   26.090652] Tap0 Sign : +
[   26.090706] tap0_coef_bin = 31
[   26.090744] tap0 manual = 0
[   26.090778] end_1.4.2
[   26.178526] 8021q: adding VLAN 0 to HW filter on device lan2
[   26.181287] switch: port 2(lan2) entered blocking state
[   26.181356] switch: port 2(lan2) entered disabled state
[   26.181467] rtl83xx-switch switch@1b000000 lan2: entered allmulticast mode
[   26.182247] rtl83xx-switch switch@1b000000 lan2: entered promiscuous mode
[   26.201651] rtl83xx-switch switch@1b000000 lan3: configuring for inband/sgmii link mode
[   26.201721] realtek-otto-pcs 1b000000.switchcore:pcs: configure SerDes 4 for mode sgmii
[   26.214507] rtpcs_930x_phy_enable_10g_1g 1gbit phy: 00001140
[   26.214571] rtpcs_930x_phy_enable_10g_1g 1gbit phy enabled: 00001140
[   26.214600] rtpcs_930x_phy_enable_10g_1g 10gbit phy: 00002040
[   26.214631] rtpcs_930x_phy_enable_10g_1g 10gbit phy after: 00002040
[   26.214661] rtpcs_930x_phy_enable_10g_1g set medium: 00000000
[   26.214690] rtpcs_930x_phy_enable_10g_1g set medium after: 00000002
[   26.214711] rtpcs_930x_setup_serdes: Configuring RTL9300 SERDES 4
[   26.214807] rtpcs_930x_sds_config_pll: SDS 4 using ring PLL for mode 5
[   26.258992] rtpcs_930x_sds_10g_idle WARNING: Waiting for RX idle timed out, SDS 4
[   26.259063] start_1.1.1 initial value for sds 4
[   26.259169] end_1.1.1 --
[   26.259201] start_1.1.2 Load DFE init. value
[   26.259253] end_1.1.2
[   26.259294] start_1.1.3 disable LEQ training,enable DFE clock
[   26.259351] end_1.1.3 --
[   26.259374] start_1.1.4 offset cali setting
[   26.259396] end_1.1.4
[   26.259411] start_1.1.5 LEQ and DFE setting
[   26.259461] end_1.1.5
[   26.265322] start_1.2.1 ForegroundOffsetCal_Manual
[   26.265393] end_1.2.1
[   26.271564] start_1.2.3 Foreground Calibration
[   26.271649] rtpcs_930x_sds_do_rx_calibration_2_3: fgcal_gray: 31, fgcal_binary 31
[   26.271689] rtpcs_930x_sds_do_rx_calibration_2_3: end_1.2.3
[   26.271708] start_1.4.1
[   26.539612] end_1.4.1
[   26.539653] start_1.4.2
[   26.540945] vth_set_bin = 7
[   26.540974] vth_set_bin = 3
[   26.540992] Vth Maunal = 0
[   26.664413] Tap0 Sign : +
[   26.664461] tap0_coef_bin = 31
[   26.664494] tap0 manual = 0
[   26.664536] end_1.4.2
[   26.749558] 8021q: adding VLAN 0 to HW filter on device lan3
[   26.751367] switch: port 3(lan3) entered blocking state
[   26.751456] switch: port 3(lan3) entered disabled state
[   26.751608] rtl83xx-switch switch@1b000000 lan3: entered allmulticast mode
[   26.752600] rtl83xx-switch switch@1b000000 lan3: entered promiscuous mode
[   26.776523] rtl83xx-switch switch@1b000000 lan4: configuring for inband/sgmii link mode
[   26.776610] realtek-otto-pcs 1b000000.switchcore:pcs: configure SerDes 5 for mode sgmii
[   26.789409] rtpcs_930x_phy_enable_10g_1g 1gbit phy: 00001140
[   26.789492] rtpcs_930x_phy_enable_10g_1g 1gbit phy enabled: 00001140
[   26.789535] rtpcs_930x_phy_enable_10g_1g 10gbit phy: 00002040
[   26.789568] rtpcs_930x_phy_enable_10g_1g 10gbit phy after: 00002040
[   26.789598] rtpcs_930x_phy_enable_10g_1g set medium: 00000000
[   26.789627] rtpcs_930x_phy_enable_10g_1g set medium after: 00000002
[   26.789651] rtpcs_930x_setup_serdes: Configuring RTL9300 SERDES 5
[   26.789728] rtpcs_930x_sds_config_pll: SDS 5 using ring PLL for mode 5
[   26.839075] rtpcs_930x_sds_10g_idle WARNING: Waiting for RX idle timed out, SDS 5
[   26.839141] start_1.1.1 initial value for sds 5
[   26.839256] end_1.1.1 --
[   26.839289] start_1.1.2 Load DFE init. value
[   26.839306] end_1.1.2
[   26.839319] start_1.1.3 disable LEQ training,enable DFE clock
[   26.839352] end_1.1.3 --
[   26.839367] start_1.1.4 offset cali setting
[   26.839385] end_1.1.4
[   26.839397] start_1.1.5 LEQ and DFE setting
[   26.839444] end_1.1.5
[   26.845381] start_1.2.1 ForegroundOffsetCal_Manual
[   26.845452] end_1.2.1
[   26.851726] start_1.2.3 Foreground Calibration
[   26.851817] rtpcs_930x_sds_do_rx_calibration_2_3: fgcal_gray: 31, fgcal_binary 31
[   26.851869] rtpcs_930x_sds_do_rx_calibration_2_3: end_1.2.3
[   26.851893] start_1.4.1
[   27.105919] end_1.4.1
[   27.105955] start_1.4.2
[   27.106991] vth_set_bin = 7
[   27.107007] vth_set_bin = 3
[   27.107019] Vth Maunal = 0
[   27.208618] Tap0 Sign : +
[   27.208651] tap0_coef_bin = 31
[   27.208669] tap0 manual = 0
[   27.208690] end_1.4.2
[   27.280456] 8021q: adding VLAN 0 to HW filter on device lan4
[   27.282282] switch: port 4(lan4) entered blocking state
[   27.282346] switch: port 4(lan4) entered disabled state
[   27.282412] rtl83xx-switch switch@1b000000 lan4: entered allmulticast mode
[   27.283048] rtl83xx-switch switch@1b000000 lan4: entered promiscuous mode
[   27.300375] rtl83xx-switch switch@1b000000 lan5: configuring for phy/usxgmii link mode
[   27.300429] realtek-otto-pcs 1b000000.switchcore:pcs: configure SerDes 9 for mode usxgmii
[   27.310840] rtpcs_930x_phy_enable_10g_1g 1gbit phy: 00001140
[   27.310886] rtpcs_930x_phy_enable_10g_1g 1gbit phy enabled: 00001140
[   27.310902] rtpcs_930x_phy_enable_10g_1g 10gbit phy: 00002040
[   27.310917] rtpcs_930x_phy_enable_10g_1g 10gbit phy after: 00002040
[   27.310933] rtpcs_930x_phy_enable_10g_1g set medium: 00000000
[   27.310948] rtpcs_930x_phy_enable_10g_1g set medium after: 00000002
[   27.310960] rtpcs_930x_setup_serdes: Configuring RTL9300 SERDES 9
[   27.331530] start_1.1.1 initial value for sds 9
[   27.331632] end_1.1.1 --
[   27.331643] start_1.1.2 Load DFE init. value
[   27.331655] end_1.1.2
[   27.331664] start_1.1.3 disable LEQ training,enable DFE clock
[   27.331687] end_1.1.3 --
[   27.331696] start_1.1.4 offset cali setting
[   27.331707] end_1.1.4
[   27.331716] start_1.1.5 LEQ and DFE setting
[   27.331724] rtpcs_930x_sds_do_rx_calibration_1 not PHY-based or SerDes, implement DAC!
[   27.340702] end_1.1.5
[   27.346178] start_1.2.1 ForegroundOffsetCal_Manual
[   27.346218] end_1.2.1
[   27.351222] start_1.2.3 Foreground Calibration
[   27.351261] rtpcs_930x_sds_do_rx_calibration_2_3: fgcal_gray: 60, fgcal_binary 34
[   27.351288] rtpcs_930x_sds_do_rx_calibration_2_3: end_1.2.3
[   27.351299] start_1.4.1
[   27.572402] end_1.4.1
[   27.572437] start_1.4.2
[   27.573472] vth_set_bin = 7
[   27.573487] vth_set_bin = 7
[   27.573498] Vth Maunal = 0
[   27.675056] Tap0 Sign : +
[   27.675089] tap0_coef_bin = 31
[   27.675106] tap0 manual = 0
[   27.675128] end_1.4.2
[   27.746879] 8021q: adding VLAN 0 to HW filter on device lan5
[   27.749959] switch: port 5(lan5) entered blocking state
[   27.750006] switch: port 5(lan5) entered disabled state
[   27.750071] rtl83xx-switch switch@1b000000 lan5: entered allmulticast mode
[   27.750748] rtl83xx-switch switch@1b000000 lan5: entered promiscuous mode
[   27.765456] rtl83xx-switch switch@1b000000 lan6: configuring for phy/usxgmii link mode
[   27.765861] realtek-otto-pcs 1b000000.switchcore:pcs: configure SerDes 8 for mode usxgmii
[   27.776320] rtpcs_930x_phy_enable_10g_1g 1gbit phy: 00001140
[   27.776367] rtpcs_930x_phy_enable_10g_1g 1gbit phy enabled: 00001140
[   27.776383] rtpcs_930x_phy_enable_10g_1g 10gbit phy: 00002040
[   27.776398] rtpcs_930x_phy_enable_10g_1g 10gbit phy after: 00002040
[   27.776414] rtpcs_930x_phy_enable_10g_1g set medium: 00000000
[   27.776429] rtpcs_930x_phy_enable_10g_1g set medium after: 00000002
[   27.776441] rtpcs_930x_setup_serdes: Configuring RTL9300 SERDES 8
[   27.797015] start_1.1.1 initial value for sds 8
[   27.797118] end_1.1.1 --
[   27.797128] start_1.1.2 Load DFE init. value
[   27.797140] end_1.1.2
[   27.797149] start_1.1.3 disable LEQ training,enable DFE clock
[   27.797171] end_1.1.3 --
[   27.797180] start_1.1.4 offset cali setting
[   27.797192] end_1.1.4
[   27.797200] start_1.1.5 LEQ and DFE setting
[   27.797209] rtpcs_930x_sds_do_rx_calibration_1 not PHY-based or SerDes, implement DAC!
[   27.806182] end_1.1.5
[   27.811563] start_1.2.1 ForegroundOffsetCal_Manual
[   27.811602] end_1.2.1
[   27.816791] start_1.2.3 Foreground Calibration
[   27.816853] rtpcs_930x_sds_do_rx_calibration_2_3: fgcal_gray: 21, fgcal_binary 31
[   27.816880] rtpcs_930x_sds_do_rx_calibration_2_3: end_1.2.3
[   27.816892] start_1.4.1
[   28.038375] end_1.4.1
[   28.038410] start_1.4.2
[   28.039444] vth_set_bin = 4
[   28.039460] vth_set_bin = 4
[   28.039471] Vth Maunal = 0
[   28.141296] Tap0 Sign : +
[   28.141330] tap0_coef_bin = 20
[   28.141348] tap0 manual = 0
[   28.141370] end_1.4.2
[   28.213315] 8021q: adding VLAN 0 to HW filter on device lan6
[   28.217187] switch: port 6(lan6) entered blocking state
[   28.217235] switch: port 6(lan6) entered disabled state
[   28.217302] rtl83xx-switch switch@1b000000 lan6: entered allmulticast mode
[   28.217970] rtl83xx-switch switch@1b000000 lan6: entered promiscuous mode
[   28.232572] rtl83xx-switch switch@1b000000 lan7: configuring for phy/usxgmii link mode
[   28.232627] realtek-otto-pcs 1b000000.switchcore:pcs: configure SerDes 7 for mode usxgmii
[   28.242900] rtpcs_930x_phy_enable_10g_1g 1gbit phy: 00001140
[   28.242942] rtpcs_930x_phy_enable_10g_1g 1gbit phy enabled: 00001140
[   28.242958] rtpcs_930x_phy_enable_10g_1g 10gbit phy: 00002040
[   28.242974] rtpcs_930x_phy_enable_10g_1g 10gbit phy after: 00002040
[   28.242989] rtpcs_930x_phy_enable_10g_1g set medium: 00000000
[   28.243005] rtpcs_930x_phy_enable_10g_1g set medium after: 00000002
[   28.243016] rtpcs_930x_setup_serdes: Configuring RTL9300 SERDES 7
[   28.263586] start_1.1.1 initial value for sds 7
[   28.263688] end_1.1.1 --
[   28.263699] start_1.1.2 Load DFE init. value
[   28.263711] end_1.1.2
[   28.263719] start_1.1.3 disable LEQ training,enable DFE clock
[   28.263743] end_1.1.3 --
[   28.263752] start_1.1.4 offset cali setting
[   28.263764] end_1.1.4
[   28.263772] start_1.1.5 LEQ and DFE setting
[   28.263780] rtpcs_930x_sds_do_rx_calibration_1 not PHY-based or SerDes, implement DAC!
[   28.272756] end_1.1.5
[   28.278284] start_1.2.1 ForegroundOffsetCal_Manual
[   28.278324] end_1.2.1
[   28.283328] start_1.2.3 Foreground Calibration
[   28.283367] rtpcs_930x_sds_do_rx_calibration_2_3: fgcal_gray: 17, fgcal_binary 25
[   28.283394] rtpcs_930x_sds_do_rx_calibration_2_3: end_1.2.3
[   28.283405] start_1.4.1
[   28.504538] end_1.4.1
[   28.504571] start_1.4.2
[   28.505736] vth_set_bin = 5
[   28.505783] vth_set_bin = 5
[   28.505805] Vth Maunal = 0
[   28.607603] Tap0 Sign : +
[   28.607638] tap0_coef_bin = 18
[   28.607656] tap0 manual = 0
[   28.607679] end_1.4.2
[   28.679395] 8021q: adding VLAN 0 to HW filter on device lan7
[   28.682910] switch: port 7(lan7) entered blocking state
[   28.682956] switch: port 7(lan7) entered disabled state
[   28.683020] rtl83xx-switch switch@1b000000 lan7: entered allmulticast mode
[   28.683656] rtl83xx-switch switch@1b000000 lan7: entered promiscuous mode
[   28.698009] rtl83xx-switch switch@1b000000 lan8: configuring for phy/usxgmii link mode
[   28.698064] realtek-otto-pcs 1b000000.switchcore:pcs: configure SerDes 6 for mode usxgmii
[   28.708482] rtpcs_930x_phy_enable_10g_1g 1gbit phy: 00001140
[   28.708528] rtpcs_930x_phy_enable_10g_1g 1gbit phy enabled: 00001140
[   28.708544] rtpcs_930x_phy_enable_10g_1g 10gbit phy: 00002040
[   28.708560] rtpcs_930x_phy_enable_10g_1g 10gbit phy after: 00002040
[   28.708575] rtpcs_930x_phy_enable_10g_1g set medium: 00000000
[   28.708591] rtpcs_930x_phy_enable_10g_1g set medium after: 00000002
[   28.708603] rtpcs_930x_setup_serdes: Configuring RTL9300 SERDES 6
[   28.729083] start_1.1.1 initial value for sds 6
[   28.729185] end_1.1.1 --
[   28.729196] start_1.1.2 Load DFE init. value
[   28.729208] end_1.1.2
[   28.729216] start_1.1.3 disable LEQ training,enable DFE clock
[   28.729239] end_1.1.3 --
[   28.729248] start_1.1.4 offset cali setting
[   28.729260] end_1.1.4
[   28.729268] start_1.1.5 LEQ and DFE setting
[   28.729277] rtpcs_930x_sds_do_rx_calibration_1 not PHY-based or SerDes, implement DAC!
[   28.738232] end_1.1.5
[   28.743612] start_1.2.1 ForegroundOffsetCal_Manual
[   28.743650] end_1.2.1
[   28.748839] start_1.2.3 Foreground Calibration
[   28.748899] rtpcs_930x_sds_do_rx_calibration_2_3: fgcal_gray: 23, fgcal_binary 28
[   28.748926] rtpcs_930x_sds_do_rx_calibration_2_3: end_1.2.3
[   28.748938] start_1.4.1
[   28.970153] end_1.4.1
[   28.970190] start_1.4.2
[   28.971224] vth_set_bin = 3
[   28.971239] vth_set_bin = 3
[   28.971251] Vth Maunal = 0
[   29.072826] Tap0 Sign : +
[   29.072860] tap0_coef_bin = 24
[   29.072877] tap0 manual = 0
[   29.072900] end_1.4.2
[   29.144621] 8021q: adding VLAN 0 to HW filter on device lan8
[   29.147580] switch: port 8(lan8) entered blocking state
[   29.147629] switch: port 8(lan8) entered disabled state
[   29.147696] rtl83xx-switch switch@1b000000 lan8: entered allmulticast mode
[   29.148335] rtl83xx-switch switch@1b000000 lan8: entered promiscuous mode
[   31.857604] rtl83xx-switch switch@1b000000 lan7: Link is Up - 1Gbps/Full - flow control rx/tx
[   31.857711] switch: port 7(lan7) entered blocking state
[   31.857744] switch: port 7(lan7) entered forwarding state
[  148.336590] rtl83xx-switch switch@1b000000 lan7: Link is Down
[  148.336911] switch: port 7(lan7) entered disabled state
[  150.497584] rtl83xx-switch switch@1b000000 lan5: Link is Up - 1Gbps/Full - flow control rx/tx
[  150.497713] switch: port 5(lan5) entered blocking state
[  150.497751] switch: port 5(lan5) entered forwarding state
[  160.896479] rtl83xx-switch switch@1b000000 lan5: Link is Down
[  160.896795] switch: port 5(lan5) entered disabled state
[  163.457610] rtl83xx-switch switch@1b000000 lan6: Link is Up - 1Gbps/Full - flow control rx/tx
[  163.457739] switch: port 6(lan6) entered blocking state
[  163.457776] switch: port 6(lan6) entered forwarding state
[  173.856446] rtl83xx-switch switch@1b000000 lan6: Link is Down
[  173.856835] switch: port 6(lan6) entered disabled state
[  176.417587] rtl83xx-switch switch@1b000000 lan7: Link is Up - 1Gbps/Full - flow control rx/tx
[  176.417718] switch: port 7(lan7) entered blocking state
[  176.417756] switch: port 7(lan7) entered forwarding state
[  182.656448] rtl83xx-switch switch@1b000000 lan7: Link is Down
[  182.656665] switch: port 7(lan7) entered disabled state
[  185.217587] rtl83xx-switch switch@1b000000 lan8: Link is Up - 1Gbps/Full - flow control rx/tx
[  185.217715] switch: port 8(lan8) entered blocking state
[  185.217752] switch: port 8(lan8) entered forwarding state
[  196.309082] sfp sfp-p1: module DELL             FCLF8521P2BTL-DL rev A0   sn N3BCC58          dc 200319  
[  196.593612] rtl83xx-switch switch@1b000000 lan1: PHY [smbus:sfp-p1:16] driver [Marvell 88E1111] (irq=POLL)
[  201.856552] rtl83xx-switch switch@1b000000 lan8: Link is Down
[  201.856764] switch: port 8(lan8) entered disabled state
[  203.861189] rtl83xx-switch switch@1b000000 lan1: Link is Up - 1Gbps/Full - flow control rx/tx
[  203.861315] switch: port 1(lan1) entered blocking state
[  203.861354] switch: port 1(lan1) entered forwarding state
[  215.608631] rtl83xx-switch switch@1b000000 lan1: Link is Down
[  215.608856] switch: port 1(lan1) entered disabled state
[  215.835979] sfp sfp-p1: module removed
[  219.159391] sfp sfp-p2: module DELL             FCLF8521P2BTL-DL rev A0   sn N3BCC58          dc 200319  
[  219.444004] rtl83xx-switch switch@1b000000 lan2: PHY [smbus:sfp-p2:16] driver [Marvell 88E1111] (irq=POLL)
[  224.661169] rtl83xx-switch switch@1b000000 lan2: Link is Up - 1Gbps/Full - flow control rx/tx
[  224.661294] switch: port 2(lan2) entered blocking state
[  224.661331] switch: port 2(lan2) entered forwarding state
[  235.792171] rtl83xx-switch switch@1b000000 lan2: Link is Down
[  235.792371] switch: port 2(lan2) entered disabled state
[  236.165972] sfp sfp-p2: module removed
[  238.279539] sfp sfp-p3: module DELL             FCLF8521P2BTL-DL rev A0   sn N3BCC58          dc 200319  
[  238.563139] rtl83xx-switch switch@1b000000 lan3: PHY [smbus:sfp-p3:16] driver [Marvell 88E1111] (irq=POLL)
[  242.741334] rtl83xx-switch switch@1b000000 lan3: Link is Up - 1Gbps/Full - flow control rx/tx
[  242.741440] switch: port 3(lan3) entered blocking state
[  242.741472] switch: port 3(lan3) entered forwarding state
[  254.973933] rtl83xx-switch switch@1b000000 lan3: Link is Down
[  254.974157] switch: port 3(lan3) entered disabled state
[  255.276077] sfp sfp-p3: module removed
[  257.499803] sfp sfp-p4: module DELL             FCLF8521P2BTL-DL rev A0   sn N3BCC58          dc 200319  
[  257.783491] rtl83xx-switch switch@1b000000 lan4: PHY [smbus:sfp-p4:16] driver [Marvell 88E1111] (irq=POLL)
[  261.941272] rtl83xx-switch switch@1b000000 lan4: Link is Up - 1Gbps/Full - flow control rx/tx
[  261.941398] switch: port 4(lan4) entered blocking state
[  261.941435] switch: port 4(lan4) entered forwarding state

plappermaul · March 14, 2026, 7:55pm

RTL8261 is provided by our downstream RTL826x driver. That is copied 1:1 from Realtek SDK and with lots of patching it should setup the PHY just fine. XGS1250-B1 uses the same PHY and they seem to work (at least I have no other info).

So start with simple things. Do you get a link up/down message when (dis)connecting cables of the RTL8261?

plappermaul · March 14, 2026, 7:59pm

P.S. We are even setting up RTL8261 PHY specific polling so that the SoC can identify what is going on See https://github.com/openwrt/openwrt/blob/3c3e56afca1e2b2c3e0c091da77bc9774c788ae3/target/linux/realtek/files-6.12/drivers/net/mdio/mdio-realtek-otto.c#L637

andyboeh · March 14, 2026, 8:11pm

Yes, link up/down events are properly reported. This points more towards the SerDes-setup then?

plappermaul · March 14, 2026, 8:21pm

That is usually the case. Just for reference

check PHY link speed with ethtool and
look at register MAC_LINK_SPD_STS with devmem https://svanheule.net/realtek/longan/register/mac_link_spd_sts.

If all that reports proper data, then PHY works as expected and background hardware polling will inform DSA about the current state. If no data passes than PHY<->SERDES link does not work as expected.

Post a serdes register dump via debugfs/realtek_serdes/serdes.X/registers. This will help Jonas to identify what is going on here.

andyboeh · March 14, 2026, 8:29pm

ethtool output is looking fine:

Settings for lan6:
        Supported ports: [ TP MII ]
        Supported link modes:   100baseT/Half 100baseT/Full 
                                1000baseT/Full 
                                10000baseT/Full 
                                2500baseT/Full 
                                5000baseT/Full 
        Supported pause frame use: Symmetric Receive-only
        Supports auto-negotiation: Yes
        Supported FEC modes: Not reported
        Advertised link modes:  100baseT/Half 100baseT/Full 
                                1000baseT/Full 
                                10000baseT/Full 
                                2500baseT/Full 
                                5000baseT/Full 
        Advertised pause frame use: Symmetric Receive-only
        Advertised auto-negotiation: Yes
        Advertised FEC modes: Not reported
        Link partner advertised link modes:  10baseT/Half 10baseT/Full 
                                             100baseT/Half 100baseT/Full 
                                             1000baseT/Full 
        Link partner advertised pause frame use: Symmetric Receive-only
        Link partner advertised auto-negotiation: Yes
        Link partner advertised FEC modes: Not reported
        Speed: 1000Mb/s
        Duplex: Full
        Port: Twisted Pair
        PHYAD: 26
        Transceiver: external
        Auto-negotiation: on
        MDI-X: off (auto)
        Supports Wake-on: d
        Wake-on: d
        Link detected: yes

I'll need to rebuild/reflash with devmem enabled. In the meantime, the serdes registers (this should be SerDes 8, at least that's what I've defined in the DTS and what should be correct according to the hardware profile).

root@OpenWrt:/sys/kernel/debug/realtek_otto_serdes/serdes.8# cat registers 
Back SDS 08:   00   01   02   03   04   05   06   07   08   09   0A   0B   0C   0D   0E   0F   10   11   12   13   14   15   16   17   18   19   1A   1B   1C   1D   1E   1F
SDS        : 1403 0F00 70D0 3106 0749 8E00 8F5F 1359 524B F000 8BA4 0000 08E4 4636 2053 0000 0000 0000 0000 4001 0001 4001 9800 9800 001C 001C 3810 0003 C040 0016 0000 0000 
SDS_EXT    : 0000 0000 0000 0000 0000 0000 0000 0003 283F 4000 0000 0000 0004 326A 0332 1162 2ABD 0000 0000 0000 0000 0000 0000 0000 0015 02BC 0000 0000 0000 0100 0100 0000 
FIB        : 0140 6109 3380 02A0 01A0 0000 0000 0004 0000 0000 0000 0000 0000 0000 0000 8000 0083 0000 5000 0000 0000 0000 0001 4001 0004 326A 0000 115D 33FA E46A 071E 0000 
FIB_EXT    : 1140 6109 3380 02A0 01A0 0000 0000 0004 0000 0000 0000 0000 0000 0000 0000 8000 02D6 0000 0124 031B 1F33 4000 0000 1408 0000 1005 0001 0000 0000 0000 0000 0000 
DTE        : 2040 0004 0000 0000 0001 002A 0000 0000 8001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
DTE_EXT    : 100D 8000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
TGX        : 0000 C800 0000 C45C 6EAA E1A8 6473 2303 7670 0000 0000 0000 0000 0F00 055A 5A5A 432E 00A8 00A4 68C1 F021 E6C4 65C5 A29B 3D79 8040 0000 0000 0000 0600 0000 0000 
TGX_EXT    : 0000 0000 0000 0000 0000 0000 1401 0000 0000 0000 0000 0000 0000 1711 1516 783F 6003 054F 0FFF 0000 0000 0000 0000 0000 0000 0000 8000 0000 0000 0000 FC14 0000 
ANA_RG     : 2040 0000 0000 0000 0001 0028 0000 0000 8000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0010 0000 0000 0000 0800 0000 0000 0000 0000 0000 0000 0000 
ANA_RG_EXT : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
ANA_TG     : 0007 0300 8000 0000 0000 0000 B6B5 0000 0000 0000 0000 0000 0000 0000 0332 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
ANA_TG_EXT : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 0C    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0003 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 0D    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 0E    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 0F    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 10    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 11    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 12    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 13    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 14    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 15    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 16    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 17    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 18    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 19    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 1A    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 1B    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 1C    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 1D    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 1E    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
ANA_WDIG   : 0000 0000 002F 0000 0000 0000 0C04 DC05 0603 0000 0000 0002 A05A 0708 0001 0000 0000 0000 0000 0000 0016 2000 B5AD 0000 0000 0000 0000 0000 0000 0000 0000 0000 
ANA_MISC   : 0000 0000 0000 0000 A05A 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
ANA_COM    : 0000 FFFF 03C0 8206 F0F0 40B0 0810 F09F 0000 FFFF 0003 0005 0007 6009 0000 0008 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
ANA_SP     : A668 2088 D020 5F5F 08C0 1000 C000 4820 23FF F000 1000 1893 2427 0BFF 0000 FFDF 2BFF 8280 0484 0264 1311 62C1 00CB A100 BE48 03E0 0001 FFFF 0400 0000 07F8 8888 
ANA_SP_EXT : 820F 0300 1017 FFD6 0000 7F7C 0200 8104 0001 FFD4 7C2F 7807 0000 0000 003F 0121 0020 8840 0000 0050 2008 8000 4000 4104 8E88 4902 A12B 0003 7109 66E1 6E30 3524 
ANA_1G     : 8360 2088 F020 5F5F 08C0 1000 E000 4820 23FF F000 1000 188A 2427 0BFF 0000 BFDF 2BFF 8280 0084 227F 2179 60C1 00CB 0100 BE48 0000 0000 FFFF 4400 0000 07F8 8888 
ANA_1G_EXT : 820F 0100 1107 FFD0 0000 787C 0200 8104 0003 FFC4 7C4F 7C07 0000 0000 FFFF F8A1 0028 8030 0000 0034 2008 8000 4000 4105 8F88 490A A02B 0003 7109 2500 5030 2624 
ANA_2G     : 8360 2088 F020 5F5F 08C0 1000 E000 4820 23FF F000 1000 188A 2427 0BFF 0000 BFDF 2BFF 8280 0084 227F 2179 60C1 00CB 0100 BE48 0000 0000 FFFF 4400 0000 07F8 8888 
ANA_2G_EXT : 820F 0100 1107 FFD0 0000 787C 0200 8104 0003 FFC4 7C4F 7C07 0000 0000 FFFF F8A1 0028 8030 0000 0034 2008 8000 4000 4105 8F88 490A A02B 0003 7109 2500 5030 2624 
ANA_3G     : 8360 2088 F020 5F5F 08C0 1000 E000 4820 23FF F000 1000 188A 2427 0BFF 0000 BFDF 2BFF 8280 0084 227F 2179 60C1 00CB 0100 BE48 0000 0000 FFFF 4400 0000 07F8 8888 
ANA_3G_EXT : 820F 0100 1107 FFD0 0000 787C 0200 8104 0003 FFC4 7C4F 7C07 0000 0000 FFFF F8A1 0028 8030 0000 0034 2008 8000 4000 4105 8F88 490A A02B 0003 7109 2640 6430 3024 
ANA_5G     : 8360 2088 F020 5F5F 08C0 1000 E000 4820 23FF F000 1000 188A 2427 0BFF 0000 BFDF 2BFF 8280 0084 227F 2179 60C1 00CB 0100 BE48 0000 0000 FFFF 4400 0000 07F8 8888 
ANA_5G_EXT : 820F 0100 1107 FFD0 0000 787C 0200 8104 0003 FFC4 7C4F 7C07 0000 0000 FFFF F8A1 0028 8030 0000 0050 2008 8000 4000 4105 8E88 4902 A02B 0003 7109 2501 5030 2624 
ANA_6G     : 8360 2088 F020 5F5F 08C0 1000 E000 4820 23FF F000 1000 188A 2427 0BFF 0000 BFDF 2BFF 8280 0084 227F 2179 60C1 00CB 0100 BE48 0000 0000 FFFF 4400 0000 07F8 8888 
ANA_6G_EXT : 820F 0100 1107 FFD0 0000 787C 0200 8104 0003 FFC4 7C4F 7C07 0000 0000 FFFF F8A1 0028 8030 0000 0050 2008 8000 4000 4105 8E88 4902 A02B 0003 7109 2641 6430 3024 
ANA_10G    : A668 2088 D020 5F5F 08C0 1000 C000 4820 23FF F000 1000 1893 2427 0BFF 0000 FFDF 2BFF 8280 0484 0264 1311 62C1 00CB A100 BE48 03E0 0001 FFFF 0400 0000 07F8 8888 
ANA_10G_EXT: 820F 0300 1017 FFD6 0000 7F7C 0200 8104 0001 FFD4 7C2F 7807 0000 0000 003F 0121 0020 8840 0000 0050 2008 8000 4000 4104 8E88 4902 A12B 0003 7109 66E1 6E30 3524 
PAGE 30    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 31    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 32    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 33    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 34    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 35    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 36    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 37    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 38    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 39    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 3A    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 3B    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 3C    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 3D    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 3E    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 
PAGE 3F    : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

plappermaul · March 14, 2026, 8:37pm

@jonasj From a quick look I'm missing the "using ... PLL" log for SerDes 8. Like this:

[    8.377375] rtpcs_930x_setup_serdes: Configuring RTL9300 SERDES 2
[    8.377444] rtpcs_930x_sds_config_pll: SDS 2 using ring PLL for mode 2

plappermaul · March 14, 2026, 8:40pm

P.S. @jonasj latest serdes patches were just merged. Maybe try a rebase. and repost log.

jonasj · March 14, 2026, 8:43pm

This should only show up for modes SGMII, 1000Base-X, 2500Base-X and 10GBase-R, other modes go the "simple" way of setting the mode, without the complex procedure ... though am more and more questioning if there really is an easy setup or we just assumed so because a lot relies on U-boot setup.

EDIT: I'll look at the logs and dumps here and respond back.

plappermaul · March 14, 2026, 8:46pm

Whereever I look around in the hardware descriptors I see RTK_MII_USXGMII_10GSXGMII for RTL8261. So setting USXGMII single link mode should be ok.

andyboeh · March 14, 2026, 8:47pm

I can also provide a dump with rtk network on and without, it will be an initramfs boot. I'm currently compiling the rebased main, then I can do the comparison.

plappermaul · March 14, 2026, 8:52pm

Additional info. The SerDes mode of the RTL8261 is needed to get a complete picture. Should be some simple mdio mmd commands. See https://github.com/plappermaul/realtek-doc/blob/8a30e593a8c666ff558a0cf9eee3653fbcf5a53d/sources/rtk-dms1250/src/hal/phy/phy_rtl826x.c#L4229