Adding Support for Xiaomi AX3000T (RD03V2)

It is not clear:

  1. Why dp2 doesn't start with 2500 speed. It seems that a deeper look into the driver code is required.
  2. ethttol shows that eth0 and eth1 are never up together. A question for the ipq experts (@robimarko, @georgem83) - should the switch function with only one (of two) successful CPU connection? The dts with my comments is in the post above.

I have no clue what the driver for that AN8855 switch is, but if its DSA based then only one CPU port is supported

Thanks. The AN8855 driver supports DSA (I've taken it from the mediatek/filogic target). Do you have any ideas why dp2 can't start at 2500 speed: swphy: unknown speed?

Stock fw supports 2500 speed (clock 312500000):

root@XiaoQiang:/# cat /sys/kernel/debug/clk/clk_summary | grep gmac
    gmac1_tx_clk_src                      1            1   312500000          0 0
       gmac1_tx_div_clk_src               2            2   312500000          0 0
          gcc_gmac1_tx_clk                2            2   312500000          0 0
    gmac1_rx_clk_src                      1            1   312500000          0 0
       gmac1_rx_div_clk_src               2            2   312500000          0 0
          gcc_gmac1_rx_clk                2            2   312500000          0 0
    gmac0_rx_clk_src                      1            1   125000000          0 0
       gmac0_rx_div_clk_src               2            2   125000000          0 0
          gcc_gmac0_rx_clk                2            2   125000000          0 0
    gmac0_tx_clk_src                      1            1   125000000          0 0
       gmac0_tx_div_clk_src               2            2   125000000          0 0
          gcc_gmac0_tx_clk                2            2   125000000          0 0
          gmac_clk_src                    9            9   240000000          0 0
             gcc_gmac0_cfg_clk            1            1   240000000          0 0
             gcc_gmac0_ptp_clk            1            1   240000000          0 0
             gcc_gmac0_sys_clk            0            0   240000000          0 0
             gcc_gmac1_cfg_clk            1            1   240000000          0 0
             gcc_gmac1_ptp_clk            1            1   240000000          0 0
             gcc_gmac1_sys_clk            1            1   240000000          0 0
             gcc_snoc_gmac0_ahb_clk           1            1   240000000          0 0
             gcc_snoc_gmac0_axi_clk           1            1   240000000          0 0
             gcc_snoc_gmac1_ahb_clk           1            1   240000000          0 0
             gcc_snoc_gmac1_axi_clk           1            1   240000000          0 0

No clue really as QCA8081 works at 2.5G so this should work as well

@csharper2005 just wondering. Any thoughts/ideas etc or is this at a deadend for v2?

Asking selfishly because 1 of the devices I was shipped is a v2 …

I changed switch CPU port from 5 to 4 and got WAN port working. LAN - not. I expect progress with this device to be slow. And in any case there will be a deadend with the wireless. 256 MB is insufficiently for Qualcomm drivers.

1 Like

Follow the picture of internal hardware. And ICs partnumber

IC1: Qualcomm IPQ5018 (CPU)
IC2: Rayson, RS128M16V8DB-107AT (RAM)
IC3: ESMT F50D1G41LB (ROM)
IC4: Airoha AN8855HN, 2521-ACSL (Ethernet)
IC5: Qualcomm QCN6102-001 (WiFi)

The UART pins are the same as V1 and is read only.

On the boot read only mode the RAM appers to be 256 MB even the chip part number with RS128M16V8DB.

(...) U-Boot 2016.01 (Feb 08 2025 - 08:05:42 +0000), Build: jenkins-common_router_openwrt_ota_publish-8537

DRAM: smem ram ptable found: ver: 1 len: 4
256 MiB (...)

I could not enable SSH yet

Still can't get the AN8855 switch CPU port to work (tried SGMII, 1000base-x, 2500base-x etc mode). I can see just the following packets every ~0.033 seconds on the switch ports:

60 bytes on wire (480 bits), 60 bytes captured (480 bits) on interface \Device\NPF, id 0
Ethernet II, Src: 00:00:00_17:a5:01 (00:00:00:17:a5:01), Dst: MAC-specific-ctrl-proto-01 (01:80:c2:00:00:01)
    Destination: MAC-specific-ctrl-proto-01 (01:80:c2:00:00:01)
        .... ..0. .... .... .... .... = LG bit: Globally unique address (factory default)
        .... ...1 .... .... .... .... = IG bit: Group address (multicast/broadcast)
    Source: 00:00:00_17:a5:01 (00:00:00:17:a5:01)
        .... ..0. .... .... .... .... = LG bit: Globally unique address (factory default)
        .... ...0 .... .... .... .... = IG bit: Individual address (unicast)
    Type: MAC Control (0x8808)
    [Stream index: 0]
MAC Control
    Opcode: Pause (0x0001)
    pause_time: 65535

That's a 2Gbit chip, divide by 8, get 256MB.

I’m trying to find out what can be done with an other Xiaomi device CPE 5G Pro.

It is based on same IPQ5018 processor. Trouble is, there is no U-boot output by UART. I suppose it is cut by manufacturer.

I quess if it would be good idea to try flashing “SBL” from AX3000 or other IPQ5018 based device to try what can be done by it.

Only I do not have a proper FW copy to try this.

So - is there someone kind enough to take a copy of the start of the NAND from a device, where UART output is on, please?

I would like to try it.

It's not, unless you want a brick.

This is a different device, and the fact that it contains 5g modem hardware strongly suggests that it's a very different device. NAND isn't easily reflashed externally, nor has ipq50xx a convenient way to recover (as mediatek/ filogic would have via mtkuart), if you break it (and that includes secure boot and signed bootloaders, including SBL!), it will be broken for good. Please start a new thread for that device (again, RAM size is paramount, anything below 512 MB is an immediate disqualification), it will need its own discovery.