My current image boots reproducibly. I’ll stop for tonight and will continue tomorrow.
@jonasj would it make sense to rebase my patch on the current main branch? I’m still at f948f71300a9f9685a6bbb7dfd742ed64892a86c (“qualcommax: ipq50xx: Add support for Zyxel SCR50AXE”) on which your previous xs1930 tree was based.
@jonasj Are there any debug commands I can execute?
The patch with the __init marker removal which seems to fix the kernel crashes:
diff --git a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c
index 787ceda834..1f0578ebba 100644
--- a/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c
+++ b/target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c
@@ -255,7 +255,7 @@ static int rtldsa_bus_c45_write(struct mii_bus *bus, int addr, int devad, int re
return mdiobus_c45_write_nested(priv->parent_bus, addr, devad, regnum, val);
}
-static int __init rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv)
+static int rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv)
{
struct device_node *dn, *phy_node, *pcs_node, *led_node, *np, *mii_np;
struct device *dev = priv->dev;
@@ -405,7 +405,7 @@ static int __init rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv)
return 0;
}
-static int __init rtl83xx_get_l2aging(struct rtl838x_switch_priv *priv)
+static int rtl83xx_get_l2aging(struct rtl838x_switch_priv *priv)
{
int t = sw_r32(priv->r->l2_ctrl_1);
@@ -1391,7 +1391,7 @@ static int rtldsa_ethernet_loaded(struct platform_device *pdev)
return ret;
}
-static int __init rtl83xx_sw_probe(struct platform_device *pdev)
+static int rtl83xx_sw_probe(struct platform_device *pdev)
{
struct rtl838x_switch_priv *priv;
struct device *dev = &pdev->dev;
diff --git a/target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.c
index 90c98f83b0..5048935ae8 100644
--- a/target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.c
+++ b/target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.c
@@ -1647,7 +1647,7 @@ static const struct ethtool_ops rteth_ethtool_ops = {
.set_link_ksettings = rteth_set_link_ksettings,
};
-static int __init rtl838x_eth_probe(struct platform_device *pdev)
+static int rtl838x_eth_probe(struct platform_device *pdev)
{
struct net_device *dev;
struct device_node *dn = pdev->dev.of_node;
Removing the __init seems worth a PR, from your explanation this is probably the reason for these "weird" crashes. None of our newer drivers uses this __init.
Non-working copper is expected for now because of the missing PCS setup. Your log doesn't show that the PHYs are recognized but I guess you commented them for now?
For the SFP, there are two reasons now why this might fail:
If they are gated, apparently the GPIOs seem different. I see you included the GPIO stuff from my DTS as-is and it doesn't seem to work. Not sure how they did it on board but if specific GPIOs aren't pulled correctly, modules cannot even respond to I2C requests.
Not in particular for your current state as there haven't been noticeable changes since then. But in general it's a good idea to keep it close to main.
f you haven't already, include gpiod-tools, i2c-tools, mdio-tools in your image to have the most important tools for debugging on the device. Also include devmem from busybox utilities and select /dev/mem support in the kernel options. Then you can read the normal registers at runtime (luckily we have the full RTL931x register file as a reference)
For the SerDes registers, there's the debugfs at /sys/kernel/debug/realtek-otto-serdes/serdes.X/registers.
For the GPIO/I2C/SFP issues, gpiod-tools and i2c-tools are your friends. Just reaching the SFP signals is hard without such a breakout that I designed.
For PHY issues, mdio-tools is your friend. Though currently the PCS is to blame that the PHYs don't work.
Thanks, will open a PR.
Nope, not commented yet, still the old DTS. That’s why I would have expected at least something (PHY ID or similar) in the logs. Any simple kernel debug switch to crank realtek logging to the max?
I’ll look at how the XMG1915 is handling this. Maybe something in my XMG1930 is closer to the XMG1915 than to the XS1930.
Will do.
Thank you, those tips are really helpful. Would you ship one of those to Germany?
Should the PHYs be detected even if they don’t work, i.e. does detection depend on PCS?
If removing those __init declarations fixes the bootup, please send a patch. Especially when something in the module dependency queue (serdes->pcs->mdio->dsa) goes wrong, we should not crash at all.
This might be of interest too if we some day want to convert to loadable modules. Initial tries have sadly stalled https://github.com/openwrt/openwrt/pull/20860
The PHYs are probed regardless of the PCS. This is triggered in the DSA driver by registering the DSA switch. Most of the debugging output is selected by the generic debug flag for the kernel.
But to be honest, I never managed to activate that properly so my debugging is usually changing those pr_debug to pr_info or pr_err so they are printed with the default debug setting. But maybe you have more luck at increasing the debug level.
Shipping from Germany to Germany is easy :D. Drop me a private message (ideally in German) and we can negotiate this.
This is probably also the reason why all of my RTL931x devices crash as soon as one of the SMI addresses isn't correct. Highly appreciated if this gets fixed.
By the way, enabling KERNEL_SLUB_DEBUG and KERNEL_SLUB_DEBUG_ON catches some types of memory corruption very quickly. It’s one of the standard ways to track down random crashes. Yes, the images get bigger and slower, but you only need to run that very few times until you have most memory corruption bugs solved.
KERNEL_KASAN would be helpful as well, but it’s not available on MIPS.
@jonasj could you please test this patch with a known crasher (incorrect SMI address) if this fixes the crash or at least postpones it?
Thanks. Tested and it helps alot. Instead of crashing, the system just defers/drops probing of the other drivers then and keeps running instead of crashing.
Yay! Thanks for testing.
What is the easiest way to get the kernel to print all found PHY IDs? Or can I query those from userspace?
mdio to list all buses, and then mdio busname to list all phys on that bus
root@OpenWrt:~# mdio
1b000000.switchcore:mdio-controller-mii
fixed-0
realtek-serdes-mdio
root@OpenWrt:~# mdio 1b000000.switchcore:mdio-controller-mii
DEV PHY-ID LINK
0x00 0x000000c1 down
0x01 0x000000c1 down
0x04 0x000000c1 down
0x05 0x000000c1 down
0x08 0x000000c1 down
0x09 0x000000c1 down
0x0c 0x000000c1 down
0x0d 0x000000c1 down
0x10 0x000000c1 down
0x11 0x000000c1 down
0x14 0x000000c1 down
0x15 0x000000c1 down
0x18 0x000000c1 down
0x19 0x000000c1 down
0x1c 0x000000c1 down
0x1d 0x000000c1 down
root@OpenWrt:~# mdio fixed-0
DEV PHY-ID LINK
root@OpenWrt:~# mdio realtek-serdes-mdio
ERROR: Unable to read status (-122)
root@OpenWrt:~# mdio 1b000000.switchcore:mdio-controller-mii
DEV PHY-ID LINK
0x00 0x0000009a down
0x01 0x0000009a down
0x04 0x0000009a down
0x05 0x0000009a down
0x08 0x0000009a down
0x09 0x0000009a down
0x0c 0x0000009a down
0x0d 0x0000009a down
0x10 0x0000009a down
0x11 0x0000009a down
0x14 0x0000009a down
0x15 0x0000009a down
0x18 0x0000009a down
0x19 0x0000009a down
0x1c 0x0000009a down
0x1d 0x0000009a down
root@OpenWrt:~# mdio fixed-0
DEV PHY-ID LINK
root@OpenWrt:~# mdio realtek-serdes-mdio
ERROR: Unable to read status (-122)
root@OpenWrt:~# mdio 1b000000.switchcore:mdio-controller-mii
DEV PHY-ID LINK
0x00 0x0000e000 down
0x01 0x0000e000 down
0x04 0x0000e000 down
0x05 0x0000e000 down
0x08 0x0000e000 down
0x09 0x0000e000 down
0x0c 0x0000e000 down
0x0d 0x0000e000 down
0x10 0x0000e000 down
0x11 0x0000e000 down
0x14 0x0000e000 down
0x15 0x0000e000 down
0x18 0x0000e000 down
0x19 0x0000e000 down
0x1c 0x0000e000 down
0x1d 0x0000e000 down
root@OpenWrt:~# mdio 1b000000.switchcore:mdio-controller-mii
DEV PHY-ID LINK
0x00 0x00000003 down
0x01 0x00000003 down
0x04 0x00000003 down
0x05 0x00000003 down
0x08 0x00000003 down
0x09 0x00000003 down
0x0c 0x00000003 down
0x0d 0x00000003 down
0x10 0x00000003 down
0x11 0x00000003 down
0x14 0x00000003 down
0x15 0x00000003 down
0x18 0x00000003 down
0x19 0x00000003 down
0x1c 0x00000003 down
0x1d 0x00000003 down
root@OpenWrt:~# mdio 1b000000.switchcore:mdio-controller-mii
DEV PHY-ID LINK
0x00 0x0000bc09 down
0x01 0x0000bc09 down
0x04 0x0000bc09 down
0x05 0x0000bc09 down
0x08 0x0000bc09 down
0x09 0x0000bc09 down
0x0c 0x0000bc09 down
0x0d 0x0000bc09 down
0x10 0x0000bc09 down
0x11 0x0000bc09 down
0x14 0x0000bc09 down
0x15 0x0000bc09 down
0x18 0x0000bc09 down
0x19 0x0000bc09 down
0x1c 0x0000bc09 down
0x1d 0x0000bc09 down
root@OpenWrt:~# mdio 1b000000.switchcore:mdio-controller-mii
DEV PHY-ID LINK
0x00 0x00000000 down
0x01 0x00000000 down
0x04 0x00000000 down
0x05 0x00000000 down
0x08 0x00000000 down
0x09 0x00000000 down
0x0c 0x00000000 down
0x0d 0x00000000 down
0x10 0x00000000 down
0x11 0x00000000 down
0x14 0x00000000 down
0x15 0x00000000 down
0x18 0x00000000 down
0x19 0x00000000 down
0x1c 0x00000000 down
0x1d 0x00000000 down
root@OpenWrt:~# mdio 1b000000.switchcore:mdio-controller-mii
DEV PHY-ID LINK
0x00 0x00000000 down
0x01 0x00000000 down
0x04 0x00000000 down
0x05 0x00000000 down
0x08 0x00000000 down
0x09 0x00000000 down
0x0c 0x00000000 down
0x0d 0x00000000 down
0x10 0x00000000 down
0x11 0x00000000 down
0x14 0x00000000 down
0x15 0x00000000 down
0x18 0x00000000 down
0x19 0x00000000 down
0x1c 0x00000000 down
0x1d 0x00000000 down
root@OpenWrt:~# mdio 1b000000.switchcore:mdio-controller-mii
DEV PHY-ID LINK
0x00 0x00000000 up
0x01 0x00000000 up
0x04 0x00000000 up
0x05 0x00000000 up
0x08 0x00000000 up
0x09 0x00000000 up
0x0c 0x00000000 up
0x0d 0x00000000 up
0x10 0x00000000 up
0x11 0x00000000 up
0x14 0x00000000 up
0x15 0x00000000 up
0x18 0x00000000 up
0x19 0x00000000 up
0x1c 0x00000000 up
0x1d 0x00000000 up
root@OpenWrt:~# mdio 1b000000.switchcore:mdio-controller-mii
DEV PHY-ID LINK
0x00 0x00000000 down
0x01 0x00000000 down
0x04 0x00000000 down
0x05 0x00000000 down
0x08 0x00000000 down
0x09 0x00000000 down
0x0c 0x00000000 down
0x0d 0x00000000 down
0x10 0x00000000 down
0x11 0x00000000 down
0x14 0x00000000 down
0x15 0x00000000 down
0x18 0x00000000 down
0x19 0x00000000 down
0x1c 0x00000000 down
0x1d 0x00000000 down
Not really what I was hoping for. The PHY-IDs keep changing. Any ideas?
root@OpenWrt:~# find /sys/ -iname "*mdio*"|sort
/sys/bus/mdio_bus
/sys/bus/mdio_bus/devices/1b000000.switchcore:mdio-controller-mii:00
/sys/bus/mdio_bus/devices/1b000000.switchcore:mdio-controller-mii:01
/sys/bus/mdio_bus/devices/1b000000.switchcore:mdio-controller-mii:04
/sys/bus/mdio_bus/devices/1b000000.switchcore:mdio-controller-mii:05
/sys/bus/mdio_bus/devices/1b000000.switchcore:mdio-controller-mii:08
/sys/bus/mdio_bus/devices/1b000000.switchcore:mdio-controller-mii:09
/sys/bus/mdio_bus/devices/1b000000.switchcore:mdio-controller-mii:0c
/sys/bus/mdio_bus/devices/1b000000.switchcore:mdio-controller-mii:0d
/sys/bus/mdio_bus/devices/1b000000.switchcore:mdio-controller-mii:10
/sys/bus/mdio_bus/devices/1b000000.switchcore:mdio-controller-mii:11
/sys/bus/mdio_bus/devices/1b000000.switchcore:mdio-controller-mii:14
/sys/bus/mdio_bus/devices/1b000000.switchcore:mdio-controller-mii:15
/sys/bus/mdio_bus/devices/1b000000.switchcore:mdio-controller-mii:18
/sys/bus/mdio_bus/devices/1b000000.switchcore:mdio-controller-mii:19
/sys/bus/mdio_bus/devices/1b000000.switchcore:mdio-controller-mii:1c
/sys/bus/mdio_bus/devices/1b000000.switchcore:mdio-controller-mii:1d
/sys/bus/mdio_bus/devices/1b000000.switchcore:mdio-controller-mii:20
/sys/bus/mdio_bus/devices/1b000000.switchcore:mdio-controller-mii:21
/sys/bus/mdio_bus/devices/1b000000.switchcore:mdio-controller-mii:24
/sys/bus/mdio_bus/devices/1b000000.switchcore:mdio-controller-mii:25
/sys/bus/mdio_bus/devices/1b000000.switchcore:mdio-controller-mii:28
/sys/bus/mdio_bus/devices/1b000000.switchcore:mdio-controller-mii:29
/sys/bus/mdio_bus/devices/1b000000.switchcore:mdio-controller-mii:2c
/sys/bus/mdio_bus/devices/1b000000.switchcore:mdio-controller-mii:2d
/sys/bus/mdio_bus/devices/1b000000.switchcore:mdio-controller-mii:30
/sys/bus/mdio_bus/devices/1b000000.switchcore:mdio-controller-mii:32
/sys/bus/mdio_bus/devices/1b000000.switchcore:mdio-controller-mii:34
/sys/bus/mdio_bus/devices/1b000000.switchcore:mdio-controller-mii:35
/sys/bus/platform/devices/1b000000.switchcore:mdio-controller
/sys/bus/platform/devices/1b000000.switchcore:mdio-serdes
/sys/bus/platform/devices/Fixed MDIO bus.0
/sys/bus/platform/drivers/mdio-rtl-otto
/sys/bus/platform/drivers/mdio-rtl-otto/1b000000.switchcore:mdio-controller
/sys/bus/platform/drivers/realtek-otto-aux-mdio
/sys/bus/platform/drivers/realtek-otto-serdes-mdio
/sys/bus/platform/drivers/realtek-otto-serdes-mdio/1b000000.switchcore:mdio-serdes
/sys/class/mdio_bus
/sys/class/mdio_bus/1b000000.switchcore:mdio-controller-mii
/sys/class/mdio_bus/realtek-serdes-mdio
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus/1b000000.switchcore:mdio-controller-mii
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus/1b000000.switchcore:mdio-controller-mii/1b000000.switchcore:mdio-controller-mii:00
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus/1b000000.switchcore:mdio-controller-mii/1b000000.switchcore:mdio-controller-mii:01
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus/1b000000.switchcore:mdio-controller-mii/1b000000.switchcore:mdio-controller-mii:04
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus/1b000000.switchcore:mdio-controller-mii/1b000000.switchcore:mdio-controller-mii:05
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus/1b000000.switchcore:mdio-controller-mii/1b000000.switchcore:mdio-controller-mii:08
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus/1b000000.switchcore:mdio-controller-mii/1b000000.switchcore:mdio-controller-mii:09
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus/1b000000.switchcore:mdio-controller-mii/1b000000.switchcore:mdio-controller-mii:0c
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus/1b000000.switchcore:mdio-controller-mii/1b000000.switchcore:mdio-controller-mii:0d
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus/1b000000.switchcore:mdio-controller-mii/1b000000.switchcore:mdio-controller-mii:10
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus/1b000000.switchcore:mdio-controller-mii/1b000000.switchcore:mdio-controller-mii:11
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus/1b000000.switchcore:mdio-controller-mii/1b000000.switchcore:mdio-controller-mii:14
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus/1b000000.switchcore:mdio-controller-mii/1b000000.switchcore:mdio-controller-mii:15
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus/1b000000.switchcore:mdio-controller-mii/1b000000.switchcore:mdio-controller-mii:18
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus/1b000000.switchcore:mdio-controller-mii/1b000000.switchcore:mdio-controller-mii:19
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus/1b000000.switchcore:mdio-controller-mii/1b000000.switchcore:mdio-controller-mii:1c
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus/1b000000.switchcore:mdio-controller-mii/1b000000.switchcore:mdio-controller-mii:1d
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus/1b000000.switchcore:mdio-controller-mii/1b000000.switchcore:mdio-controller-mii:20
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus/1b000000.switchcore:mdio-controller-mii/1b000000.switchcore:mdio-controller-mii:21
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus/1b000000.switchcore:mdio-controller-mii/1b000000.switchcore:mdio-controller-mii:24
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus/1b000000.switchcore:mdio-controller-mii/1b000000.switchcore:mdio-controller-mii:25
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus/1b000000.switchcore:mdio-controller-mii/1b000000.switchcore:mdio-controller-mii:28
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus/1b000000.switchcore:mdio-controller-mii/1b000000.switchcore:mdio-controller-mii:29
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus/1b000000.switchcore:mdio-controller-mii/1b000000.switchcore:mdio-controller-mii:2c
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus/1b000000.switchcore:mdio-controller-mii/1b000000.switchcore:mdio-controller-mii:2d
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus/1b000000.switchcore:mdio-controller-mii/1b000000.switchcore:mdio-controller-mii:30
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus/1b000000.switchcore:mdio-controller-mii/1b000000.switchcore:mdio-controller-mii:32
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus/1b000000.switchcore:mdio-controller-mii/1b000000.switchcore:mdio-controller-mii:34
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus/1b000000.switchcore:mdio-controller-mii/1b000000.switchcore:mdio-controller-mii:35
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-serdes
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-serdes/mdio_bus
/sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-serdes/mdio_bus/realtek-serdes-mdio
/sys/devices/platform/Fixed MDIO bus.0
/sys/devices/platform/Fixed MDIO bus.0/mdio_bus
/sys/firmware/devicetree/base/pinmux@1b0007d4/gpio-mdio-en
/sys/firmware/devicetree/base/pinmux@1b001358/enable-mdc-mdio-0
/sys/firmware/devicetree/base/pinmux@1b001358/enable-mdc-mdio-1
/sys/firmware/devicetree/base/pinmux@1b001358/enable-mdc-mdio-2
/sys/firmware/devicetree/base/pinmux@1b001358/enable-mdc-mdio-3
/sys/firmware/devicetree/base/switchcore@1b000000/mdio-aux
/sys/firmware/devicetree/base/switchcore@1b000000/mdio-controller
/sys/firmware/devicetree/base/switchcore@1b000000/mdio-controller/mdio-bus@0
/sys/firmware/devicetree/base/switchcore@1b000000/mdio-serdes
/sys/module/mdio_netlink
root@OpenWrt:~# cat /sys/devices/platform/1b000000.switchcore/1b000000.switchcore:mdio-controller/mdio_bus/1b000000.switchcore:mdio-controller-mii/1b000000.switchcore:mdio-controller-mii:*/phy_id
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
mdio-tools is somewhat limited here, Realtek SMI doesn't use real MDIO addresses but the port/MAC number instead. So you usually don't see all PHYs in the output. The SMI depends on the correct configuration so you cannot really scan the bus and see if you can find something somewhere.
Not sure if there's a better way but I usually added some prints to what is involved in probing the bus.
Easiest right now is probably going to the MDIO driver and use the prints (aka make them visible) e.g. in rtmdio_read_c45. Either print all or just access to the known PHY ID registers.
That did the trick.
rtmdio_931x_read_mmd_phy: port 0, dev: 1, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 0, dev: 3, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 0, dev: 4, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 0, dev: 7, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 0, dev: 1d, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 0, dev: 1e, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 1, dev: 1, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 1, dev: 3, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 1, dev: 4, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 1, dev: 7, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 1, dev: 1d, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 1, dev: 1e, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 4, dev: 1, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 4, dev: 3, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 4, dev: 4, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 4, dev: 7, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 4, dev: 1d, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 4, dev: 1e, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 5, dev: 1, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 5, dev: 3, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 5, dev: 4, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 5, dev: 7, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 5, dev: 1d, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 5, dev: 1e, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 8, dev: 1, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 8, dev: 3, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 8, dev: 4, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 8, dev: 7, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 8, dev: 1d, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 8, dev: 1e, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 9, dev: 1, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 9, dev: 3, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 9, dev: 4, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 9, dev: 7, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 9, dev: 1d, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 9, dev: 1e, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 12, dev: 1, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 12, dev: 3, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 12, dev: 4, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 12, dev: 7, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 12, dev: 1d, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 12, dev: 1e, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 13, dev: 1, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 13, dev: 3, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 13, dev: 4, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 13, dev: 7, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 13, dev: 1d, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 13, dev: 1e, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 16, dev: 1, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 16, dev: 3, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 16, dev: 4, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 16, dev: 7, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 16, dev: 1d, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 16, dev: 1e, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 17, dev: 1, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 17, dev: 3, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 17, dev: 4, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 17, dev: 7, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 17, dev: 1d, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 17, dev: 1e, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 20, dev: 1, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 20, dev: 3, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 20, dev: 4, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 20, dev: 7, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 20, dev: 1d, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 20, dev: 1e, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 21, dev: 1, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 21, dev: 3, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 21, dev: 4, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 21, dev: 7, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 21, dev: 1d, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 21, dev: 1e, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 24, dev: 1, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 24, dev: 3, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 24, dev: 4, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 24, dev: 7, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 24, dev: 1d, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 24, dev: 1e, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 25, dev: 1, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 25, dev: 3, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 25, dev: 4, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 25, dev: 7, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 25, dev: 1d, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 25, dev: 1e, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 28, dev: 1, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 28, dev: 3, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 28, dev: 4, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 28, dev: 7, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 28, dev: 1d, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 28, dev: 1e, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 29, dev: 1, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 29, dev: 3, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 29, dev: 4, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 29, dev: 7, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 29, dev: 1d, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 29, dev: 1e, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 32, dev: 1, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 32, dev: 3, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 32, dev: 4, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 32, dev: 7, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 32, dev: 1d, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 32, dev: 1e, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 33, dev: 1, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 33, dev: 3, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 33, dev: 4, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 33, dev: 7, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 33, dev: 1d, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 33, dev: 1e, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 36, dev: 1, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 36, dev: 3, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 36, dev: 4, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 36, dev: 7, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 36, dev: 1d, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 36, dev: 1e, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 37, dev: 1, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 37, dev: 3, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 37, dev: 4, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 37, dev: 7, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 37, dev: 1d, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 37, dev: 1e, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 40, dev: 1, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 40, dev: 3, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 40, dev: 4, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 40, dev: 7, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 40, dev: 1d, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 40, dev: 1e, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 41, dev: 1, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 41, dev: 3, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 41, dev: 4, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 41, dev: 7, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 41, dev: 1d, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 41, dev: 1e, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 44, dev: 1, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 44, dev: 3, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 44, dev: 4, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 44, dev: 7, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 44, dev: 1d, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 44, dev: 1e, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 45, dev: 1, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 45, dev: 3, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 45, dev: 4, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 45, dev: 7, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 45, dev: 1d, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 45, dev: 1e, regnum: 2, val: 31c3, regnum: 3, val: 1cd3
rtmdio_931x_read_mmd_phy: port 48, dev: 1, regnum: 2, val: 31c3, regnum: 3, val: 1c83
rtmdio_931x_read_mmd_phy: port 48, dev: 3, regnum: 2, val: 31c3, regnum: 3, val: 1c83
rtmdio_931x_read_mmd_phy: port 48, dev: 4, regnum: 2, val: 31c3, regnum: 3, val: 1c83
rtmdio_931x_read_mmd_phy: port 48, dev: 7, regnum: 2, val: 31c3, regnum: 3, val: 1c83
rtmdio_931x_read_mmd_phy: port 48, dev: 1d, regnum: 2, val: 31c3, regnum: 3, val: 1c83
rtmdio_931x_read_mmd_phy: port 48, dev: 1e, regnum: 2, val: 31c3, regnum: 3, val: 1c83
rtmdio_931x_read_mmd_phy: port 50, dev: 1, regnum: 2, val: 31c3, regnum: 3, val: 1c83
rtmdio_931x_read_mmd_phy: port 50, dev: 3, regnum: 2, val: 31c3, regnum: 3, val: 1c83
rtmdio_931x_read_mmd_phy: port 50, dev: 4, regnum: 2, val: 31c3, regnum: 3, val: 1c83
rtmdio_931x_read_mmd_phy: port 50, dev: 7, regnum: 2, val: 31c3, regnum: 3, val: 1c83
rtmdio_931x_read_mmd_phy: port 50, dev: 1d, regnum: 2, val: 31c3, regnum: 3, val: 1c83
rtmdio_931x_read_mmd_phy: port 50, dev: 1e, regnum: 2, val: 31c3, regnum: 3, val: 1c83
rtmdio_931x_read_mmd_phy: port 52, dev: 1, regnum: 2, val: 31c3, regnum: 3, val: 1c83
rtmdio_931x_read_mmd_phy: port 52, dev: 3, regnum: 2, val: 31c3, regnum: 3, val: 1c83
rtmdio_931x_read_mmd_phy: port 52, dev: 4, regnum: 2, val: 31c3, regnum: 3, val: 1c83
rtmdio_931x_read_mmd_phy: port 52, dev: 7, regnum: 2, val: 31c3, regnum: 3, val: 1c83
rtmdio_931x_read_mmd_phy: port 52, dev: 1d, regnum: 2, val: 31c3, regnum: 3, val: 1c83
rtmdio_931x_read_mmd_phy: port 52, dev: 1e, regnum: 2, val: 31c3, regnum: 3, val: 1c83
rtmdio_931x_read_mmd_phy: port 53, dev: 1, regnum: 2, val: 31c3, regnum: 3, val: 1c83
rtmdio_931x_read_mmd_phy: port 53, dev: 3, regnum: 2, val: 31c3, regnum: 3, val: 1c83
rtmdio_931x_read_mmd_phy: port 53, dev: 4, regnum: 2, val: 31c3, regnum: 3, val: 1c83
rtmdio_931x_read_mmd_phy: port 53, dev: 7, regnum: 2, val: 31c3, regnum: 3, val: 1c83
rtmdio_931x_read_mmd_phy: port 53, dev: 1d, regnum: 2, val: 31c3, regnum: 3, val: 1c83
rtmdio_931x_read_mmd_phy: port 53, dev: 1e, regnum: 2, val: 31c3, regnum: 3, val: 1c83
Aggregated:
rtmdio_931x_read_mmd_phy: port 0, 0x31c31cd3
rtmdio_931x_read_mmd_phy: port 1, 0x31c31cd3
rtmdio_931x_read_mmd_phy: port 4, 0x31c31cd3
rtmdio_931x_read_mmd_phy: port 5, 0x31c31cd3
rtmdio_931x_read_mmd_phy: port 8, 0x31c31cd3
rtmdio_931x_read_mmd_phy: port 9, 0x31c31cd3
rtmdio_931x_read_mmd_phy: port 12, 0x31c31cd3
rtmdio_931x_read_mmd_phy: port 13, 0x31c31cd3
rtmdio_931x_read_mmd_phy: port 16, 0x31c31cd3
rtmdio_931x_read_mmd_phy: port 17, 0x31c31cd3
rtmdio_931x_read_mmd_phy: port 20, 0x31c31cd3
rtmdio_931x_read_mmd_phy: port 21, 0x31c31cd3
rtmdio_931x_read_mmd_phy: port 24, 0x31c31cd3
rtmdio_931x_read_mmd_phy: port 25, 0x31c31cd3
rtmdio_931x_read_mmd_phy: port 28, 0x31c31cd3
rtmdio_931x_read_mmd_phy: port 29, 0x31c31cd3
rtmdio_931x_read_mmd_phy: port 32, 0x31c31cd3
rtmdio_931x_read_mmd_phy: port 33, 0x31c31cd3
rtmdio_931x_read_mmd_phy: port 36, 0x31c31cd3
rtmdio_931x_read_mmd_phy: port 37, 0x31c31cd3
rtmdio_931x_read_mmd_phy: port 40, 0x31c31cd3
rtmdio_931x_read_mmd_phy: port 41, 0x31c31cd3
rtmdio_931x_read_mmd_phy: port 44, 0x31c31cd3
rtmdio_931x_read_mmd_phy: port 45, 0x31c31cd3
rtmdio_931x_read_mmd_phy: port 48, 0x31c31c83
rtmdio_931x_read_mmd_phy: port 50, 0x31c31c83
rtmdio_931x_read_mmd_phy: port 52, 0x31c31c83
rtmdio_931x_read_mmd_phy: port 53, 0x31c31c83
Unfortunately I was completely unable to find any documentation for those PHY IDs (if they are PHY IDs). They look similar to Aquantia PHY IDs.
Now it's getting interesting 
Those are definitely Aquantia, but who knows which exactly ... based on my XS1930-10 having AQR813 and AQR113C and this "datasheet" here: https://www.marvell.com/content/dam/marvell/en/public-collateral/transceivers/marvell-phys-transceivers-aqrate-gen4-product-brief.pdf
I guess those in your device might be AQR415C. Not sure if you are fine with opening the device and (if possible) take of one of the heatsinks to see which chip there really is.
Apart from that, there's no support in the driver for this PHY ID right now. But it might be easy to add it. Somehow, I like those Aquantia PHYs, they do not cause that much problems. So I suggest to do a small driver patch adding this PHY ID and duplicating the phy_driver entry block from one of the other PHYs in there (probably AQR813) and see what works and what doesn't. These Aquantia AQRate seems to use mostly the same functions in the driver so there's a high chance this works.
Aquantia PHY IDs which are similar could be found in https://github.com/openwrt/qca-ssdk/blob/openwrt/include/hsl/phy/hsl_phy.h
#define AQUANTIA_PHY_107 0x03a1b4e2
#define AQUANTIA_PHY_108 0x03a1b4f2
#define AQUANTIA_PHY_109 0x03a1b502
#define AQUANTIA_PHY_111 0x03a1b610
#define AQUANTIA_PHY_111B0 0x03a1b612
#define AQUANTIA_PHY_112 0x03a1b660
#define AQUANTIA_PHY_112C 0x03a1b792
#define AQUANTIA_PHY_113C_A0 0x31c31C10
#define AQUANTIA_PHY_113C_A1 0x31c31C11
#define AQUANTIA_PHY_113C_B0 0x31c31C12
#define AQUANTIA_PHY_113C_B1 0x31c31C13
#define AQUANTIA_PHY_114C_B0 0x31c31c22
#define MVL_PHY_X3410 0x31c31DD3
#define PHY_ID_AQ1202 0x03a1b445
#define PHY_ID_AQ2104 0x03a1b460
#define PHY_ID_AQR105 0x03a1b4a2
#define PHY_ID_AQR106 0x03a1b4d0
#define PHY_ID_AQR107 0x03a1b4e0
#define PHY_ID_AQCS109 0x03a1b5c2
#define PHY_ID_AQR405 0x03a1b4b0
#define PHY_ID_AQR111 0x03a1b610
#define PHY_ID_AQR111B0 0x03a1b612
#define PHY_ID_AQR112 0x03a1b662
#define PHY_ID_AQR412 0x03a1b6f2
#define PHY_ID_AQR412C 0x03a1b712
#define PHY_ID_AQR113 0x31c31c40
#define PHY_ID_AQR113C 0x31c31c12
#define PHY_ID_AQR114C 0x31c31c22
#define PHY_ID_AQR115 0x31c31c63
#define PHY_ID_AQR115C 0x31c31c33
#define PHY_ID_AQR813 0x31c31cb2
and in https://github.com/Aquantia/linux-aqr-phy/blob/aqr_mainline/drivers/net/phy/aquantia/aquantia_main.c
#define PHY_ID_AQ1202 0x03a1b445
#define PHY_ID_AQ2104 0x03a1b460
#define PHY_ID_AQR105 0x03a1b4a2
#define PHY_ID_AQR106 0x03a1b4d0
#define PHY_ID_AQR107 0x03a1b4e0
#define PHY_ID_AQR108 0x03a1b4f0
#define PHY_ID_AQR109 0x03a1b500
#define PHY_ID_AQCS109 0x03a1b5c2
#define PHY_ID_AQR405 0x03a1b4b0
#define PHY_ID_AQR111 0x03a1b610
#define PHY_ID_AQR111C 0x03a1b7e0
#define PHY_ID_AQR112 0x03a1b660
#define PHY_ID_AQR112C 0x03a1b790
#define PHY_ID_AQR113 0x31c31c42
#define PHY_ID_AQR113C 0x31c31c12
#define PHY_ID_AQR114 0x31c31c52
#define PHY_ID_AQR114C 0x31c31c22
#define PHY_ID_AQR115 0x31c31c62
#define PHY_ID_AQR115C 0x31c31c32
and in https://github.com/gregkh/linux/commit/ece674102e691dcd755068dcb1f32faa72224457
#define PHY_ID_AQR113C 0x31c31c12
#define PHY_ID_AQR113C_B1 0x31c31c13
#define PHY_ID_AQR115 0x31c31c32
#define PHY_ID_AQR115_B1 0x31c31c32
#define PHY_ID_AQR115C 0x31c31c32
#define PHY_ID_AQR115C_B1 0x31c31c33
I was unable to find a datasheet with PHY IDs, though.
From the Marvell/Aquantia website, the following products may be possible matches for the PHY capabilities found in the XGS1930-30HP. I have not checked if the switch uses single-port or multi-port PHYs.
The device most likely uses four-port PHYs, as per the hardware profile I provided 4 ports are assigned to one SerDes. You can't split up a SerDes physically, and otherwise the math doesn't go right.
The PHYs you listed are older generation, see https://www.marvell.com/content/dam/marvell/en/public-collateral/transceivers/marvell-phys-transceivers-aqrate-gen2-product-brief-2019-09.pdf
Since my device has also Gen4, I suppose the XGS1930-30 uses Gen4 too.
Another hint pointing to that is that PHY IDs for Gen3 and Gen2 use a different OUI portion in the PHY ID.