Have fun with the report
Congrats Robi!
what about possibility of using the NSS to ath11k offload
1 Like
What about it?
I know that @bitthief is working on porting NSS stuff here: https://github.com/bitthief/openwrt/tree/ipq807x-5.15-pr-final but I'm still not sure how does it work, what is/can be offloaded, what are limitations
Only as curiosity... how is the process of adding a new target to make it available in OpenWrt? I can't find documentation about it.
I want to modifiy the wiki, but the target must be included in the TOH and for that, it must be added as target (now it does not appear in the combo of available targets) 
I know @Ansuel https://github.com/Ansuel/openwrt/commits/ipq807x-5.15-wifi-offload supported wifi offload,but latest pr no longer about commits of ath11k nss wifi offload
1 Like
The reason is discussed many times. NSS in general (not just wifi offload but any kind of offload) is a mess, in its current form it will not be possible to upstream it. And at this point in time it is questionable if it will ever be possible to upstream it.
I just built openwrt/openwrt master from scratch and installed onto my AX3600s without issue. compat version is obviously now 1.0 again, so the state needs to be reverted before running sysupgrade.
Thanks again!
Everything works thanks for help.
bro is there any update for your ax3600 firmware version ?? especially the increased version
and thanks for your support
if you consider this to be dumb "user question3" not worth dev forum, please ignore it.
I am trying to test VLAN functionality (check whether is affects CPU load) but I am pulling my hair as I cannot replicate setup I run in my C7. C7 has a built in VLAN-capable switch so tagging port with VLAN ID is trivial. But AX3600 does not have a switch. It has four ethernet cards and relies on CPU to do the switching.
How do I map this into AX3600 specific "CPU-switch" config (you can ignore LAN4 config as AX3600 is one port short):
(in this test, AX3600 is behaving as dumb AP and LAN 3 is supposed to be handled differently)
Thanks!
Hi,
Try searching for VLANS IN OPENWRT 21 in YouTube.
The videos from OneMarcFifty explains how to setup it on >21 versions.
1 Like
Official support is almost there - please wait a little.
can someone give me output of cat /sys/kernel/debug/clk/clk_summary
AX3600 r0-3a2144f:
root@X2:~# cat /sys/kernel/debug/clk/clk_summary
enable prepare protect duty hardware
clock count count count rate accuracy phase cycle enable
-------------------------------------------------------------------------------------------------------
uniphy2_gcc_tx_clk 1 1 0 125000000 0 0 50000 Y
nss_port6_tx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port6_tx_div_clk_src 2 2 0 125000000 0 0 50000 Y
gcc_uniphy2_port6_tx_clk 1 1 0 125000000 0 0 50000 Y
gcc_nss_port6_tx_clk 1 1 0 125000000 0 0 50000 Y
uniphy2_gcc_rx_clk 1 1 0 125000000 0 0 50000 Y
nss_port6_rx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port6_rx_div_clk_src 2 2 0 125000000 0 0 50000 Y
gcc_uniphy2_port6_rx_clk 1 1 0 125000000 0 0 50000 Y
gcc_nss_port6_rx_clk 1 1 0 125000000 0 0 50000 Y
uniphy1_gcc_tx_clk 0 0 0 125000000 0 0 50000 Y
uniphy1_gcc_rx_clk 0 0 0 125000000 0 0 50000 Y
uniphy0_gcc_tx_clk 5 5 0 125000000 0 0 50000 Y
nss_port1_tx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port1_tx_div_clk_src 2 2 0 125000000 0 0 50000 Y
gcc_uniphy0_port1_tx_clk 1 1 0 125000000 0 0 50000 Y
gcc_nss_port1_tx_clk 1 1 0 125000000 0 0 50000 Y
nss_port2_tx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port2_tx_div_clk_src 2 2 0 125000000 0 0 50000 Y
gcc_uniphy0_port2_tx_clk 1 1 0 125000000 0 0 50000 Y
gcc_nss_port2_tx_clk 1 1 0 125000000 0 0 50000 Y
nss_port3_tx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port3_tx_div_clk_src 2 2 0 125000000 0 0 50000 Y
gcc_uniphy0_port3_tx_clk 1 1 0 125000000 0 0 50000 Y
gcc_nss_port3_tx_clk 1 1 0 125000000 0 0 50000 Y
nss_port4_tx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port4_tx_div_clk_src 2 2 0 125000000 0 0 50000 Y
gcc_uniphy0_port4_tx_clk 1 1 0 125000000 0 0 50000 Y
gcc_nss_port4_tx_clk 1 1 0 125000000 0 0 50000 Y
nss_port5_tx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port5_tx_div_clk_src 3 3 0 125000000 0 0 50000 Y
gcc_uniphy1_port5_tx_clk 1 1 0 125000000 0 0 50000 Y
gcc_uniphy0_port5_tx_clk 1 1 0 125000000 0 0 50000 Y
gcc_nss_port5_tx_clk 1 1 0 125000000 0 0 50000 Y
uniphy0_gcc_rx_clk 5 5 0 125000000 0 0 50000 Y
nss_port1_rx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port1_rx_div_clk_src 2 2 0 125000000 0 0 50000 Y
gcc_uniphy0_port1_rx_clk 1 1 0 125000000 0 0 50000 Y
gcc_nss_port1_rx_clk 1 1 0 125000000 0 0 50000 Y
nss_port2_rx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port2_rx_div_clk_src 2 2 0 125000000 0 0 50000 Y
gcc_uniphy0_port2_rx_clk 1 1 0 125000000 0 0 50000 Y
gcc_nss_port2_rx_clk 1 1 0 125000000 0 0 50000 Y
nss_port3_rx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port3_rx_div_clk_src 2 2 0 125000000 0 0 50000 Y
gcc_uniphy0_port3_rx_clk 1 1 0 125000000 0 0 50000 Y
gcc_nss_port3_rx_clk 1 1 0 125000000 0 0 50000 Y
nss_port4_rx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port4_rx_div_clk_src 2 2 0 125000000 0 0 50000 Y
gcc_uniphy0_port4_rx_clk 1 1 0 125000000 0 0 50000 Y
gcc_nss_port4_rx_clk 1 1 0 125000000 0 0 50000 Y
nss_port5_rx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port5_rx_div_clk_src 3 3 0 125000000 0 0 50000 Y
gcc_uniphy1_port5_rx_clk 1 1 0 125000000 0 0 50000 Y
gcc_uniphy0_port5_rx_clk 1 1 0 125000000 0 0 50000 Y
gcc_nss_port5_rx_clk 1 1 0 125000000 0 0 50000 Y
pcie20_phy0_pipe_clk 1 1 0 250000000 0 0 50000 Y
pcie0_pipe_clk_src 1 1 0 250000000 0 0 50000 Y
gcc_pcie0_pipe_clk 1 1 0 250000000 0 0 50000 Y
bias_pll_nss_noc_clk 1 1 0 416500000 0 0 50000 Y
nss_noc_bfdcd_clk_src 1 1 0 416500000 0 0 50000 Y
nss_noc_clk_src 2 2 0 416500000 0 0 50000 Y
gcc_ubi1_nc_axi_clk 0 0 0 416500000 0 0 50000 N
gcc_ubi1_axi_clk 0 0 0 416500000 0 0 50000 N
gcc_ubi0_nc_axi_clk 0 0 0 416500000 0 0 50000 N
gcc_ubi0_axi_clk 0 0 0 416500000 0 0 50000 N
gcc_nss_noc_clk 1 1 0 416500000 0 0 50000 Y
gcc_mem_noc_nss_axi_clk 1 1 0 416500000 0 0 50000 Y
bias_pll_cc_clk 1 1 0 300000000 0 0 50000 Y
nss_ppe_clk_src 15 15 0 300000000 0 0 50000 Y
gcc_crypto_ppe_clk 0 0 0 300000000 0 0 50000 N
gcc_port6_mac_clk 1 1 0 300000000 0 0 50000 Y
gcc_port5_mac_clk 1 1 0 300000000 0 0 50000 Y
gcc_port4_mac_clk 1 1 0 300000000 0 0 50000 Y
gcc_port3_mac_clk 1 1 0 300000000 0 0 50000 Y
gcc_port2_mac_clk 1 1 0 300000000 0 0 50000 Y
gcc_port1_mac_clk 1 1 0 300000000 0 0 50000 Y
gcc_nssnoc_ppe_clk 1 1 0 300000000 0 0 50000 Y
gcc_nssnoc_ppe_cfg_clk 1 1 0 300000000 0 0 50000 Y
gcc_nss_ppe_ipe_clk 1 1 0 300000000 0 0 50000 Y
gcc_nss_ppe_clk 1 1 0 300000000 0 0 50000 Y
gcc_nss_ppe_cfg_clk 1 1 0 300000000 0 0 50000 Y
gcc_nss_ppe_btq_clk 1 1 0 300000000 0 0 50000 Y
gcc_nss_edma_clk 1 1 0 300000000 0 0 50000 Y
gcc_nss_edma_cfg_clk 1 1 0 300000000 0 0 50000 Y
nss_ppe_cdiv_clk_src 1 1 0 75000000 0 0 50000 Y
gcc_nss_ptp_ref_clk 1 1 0 75000000 0 0 50000 Y
xo 8 8 0 19200000 0 0 50000 Y
a53pll 1 1 0 1017600000 0 0 50000 Y
apcs_alias0_clk_src 1 1 0 1017600000 0 0 50000 Y
apcs_alias0_core_clk 1 1 0 1017600000 0 0 50000 Y
gp3_clk_src 0 0 0 19200000 0 0 50000 N
gcc_gp3_clk 0 0 0 19200000 0 0 50000 N
gp2_clk_src 0 0 0 19200000 0 0 50000 N
gcc_gp2_clk 0 0 0 19200000 0 0 50000 N
gp1_clk_src 0 0 0 19200000 0 0 50000 N
gcc_gp1_clk 0 0 0 19200000 0 0 50000 N
ubi_mpt_clk_src 0 0 0 19200000 0 0 50000 N
gcc_ubi1_mpt_clk 0 0 0 19200000 0 0 50000 N
gcc_ubi0_mpt_clk 0 0 0 19200000 0 0 50000 N
nss_ubi1_clk_src 0 0 0 19200000 0 0 50000 N
nss_ubi1_div_clk_src 0 0 0 19200000 0 0 50000 Y
gcc_ubi1_core_clk 0 0 0 19200000 0 0 50000 N
nss_ubi0_clk_src 0 0 0 19200000 0 0 50000 N
nss_ubi0_div_clk_src 0 0 0 19200000 0 0 50000 Y
gcc_ubi0_core_clk 0 0 0 19200000 0 0 50000 N
nss_ce_clk_src 0 0 0 19200000 0 0 50000 N
gcc_ubi1_ahb_clk 0 0 0 19200000 0 0 50000 N
gcc_ubi0_ahb_clk 0 0 0 19200000 0 0 50000 N
gcc_nssnoc_ubi1_ahb_clk 0 0 0 19200000 0 0 50000 N
gcc_nssnoc_ubi0_ahb_clk 0 0 0 19200000 0 0 50000 N
gcc_nssnoc_ce_axi_clk 0 0 0 19200000 0 0 50000 N
gcc_nssnoc_ce_apb_clk 0 0 0 19200000 0 0 50000 N
gcc_nss_csr_clk 0 0 0 19200000 0 0 50000 N
gcc_nss_ce_axi_clk 0 0 0 19200000 0 0 50000 N
gcc_nss_ce_apb_clk 0 0 0 19200000 0 0 50000 N
gcc_xo_clk_src 5 5 0 19200000 0 0 50000 Y
gcc_uniphy2_sys_clk 1 1 0 19200000 0 0 50000 Y
gcc_uniphy1_sys_clk 1 1 0 19200000 0 0 50000 Y
gcc_uniphy0_sys_clk 1 1 0 19200000 0 0 50000 Y
gcc_cmn_12gpll_sys_clk 1 1 0 19200000 0 0 50000 Y
gcc_nssnoc_qosgen_ref_clk 0 0 0 19200000 0 0 50000 N
gcc_xo_div4_clk_src 0 0 0 4800000 0 0 50000 Y
gcc_nssnoc_timeout_ref_clk 0 0 0 4800000 0 0 50000 N
usb1_aux_clk_src 0 0 0 19200000 0 0 50000 N
gcc_usb1_aux_clk 0 0 0 19200000 0 0 50000 N
usb0_aux_clk_src 0 0 0 19200000 0 0 50000 N
gcc_usb0_aux_clk 0 0 0 19200000 0 0 50000 N
sdcc2_apps_clk_src 0 0 0 19200000 0 0 50000 N
gcc_sdcc2_apps_clk 0 0 0 19200000 0 0 50000 N
sdcc1_apps_clk_src 0 0 0 19200000 0 0 50000 N
gcc_sdcc1_apps_clk 0 0 0 19200000 0 0 50000 N
pcie1_aux_clk_src 0 0 0 19200000 0 0 50000 Y
gcc_pcie1_aux_clk 0 0 0 19200000 0 0 50000 N
pcie0_aux_clk_src 1 1 0 19200000 0 0 50000 Y
gcc_pcie0_aux_clk 1 1 0 19200000 0 0 50000 Y
nss_crypto_pll_main 1 1 0 1190400000 0 0 50000 Y
nss_crypto_pll 1 1 0 595200000 0 0 50000 Y
nss_crypto_clk_src 1 1 0 595200000 0 0 50000 Y
gcc_nssnoc_crypto_clk 0 0 0 595200000 0 0 50000 N
gcc_nss_crypto_clk 1 1 0 595200000 0 0 50000 Y
ubi32_pll_main 0 0 0 1497600000 0 0 50000 N
ubi32_pll 0 0 0 1497600000 0 0 50000 Y
gpll6_main 1 1 0 1080000000 0 0 50000 Y
gpll6 0 0 0 1080000000 0 0 50000 Y
usb1_mock_utmi_clk_src 0 0 0 20000000 0 0 55555 Y
gcc_usb1_mock_utmi_clk 0 0 0 20000000 0 0 50000 N
usb0_mock_utmi_clk_src 0 0 0 20000000 0 0 55555 Y
gcc_usb0_mock_utmi_clk 0 0 0 20000000 0 0 50000 N
sdcc1_ice_core_clk_src 0 0 0 308571428 0 0 50000 N
gcc_sdcc1_ice_core_clk 0 0 0 308571428 0 0 50000 N
gpll6_out_main_div2 0 0 0 540000000 0 0 50000 Y
gpll4_main 1 1 0 1200000000 0 0 50000 Y
gpll4 0 0 0 1200000000 0 0 50000 Y
gpll2_main 1 1 0 1152000000 0 0 50000 Y
gpll2 0 0 0 1152000000 0 0 50000 Y
blsp1_uart6_apps_clk_src 0 0 0 19200000 0 0 50000 N
gcc_blsp1_uart6_apps_clk 0 0 0 19200000 0 0 50000 N
blsp1_uart4_apps_clk_src 0 0 0 19200000 0 0 50000 N
gcc_blsp1_uart4_apps_clk 0 0 0 19200000 0 0 50000 N
blsp1_uart3_apps_clk_src 0 0 0 19200000 0 0 50000 N
gcc_blsp1_uart3_apps_clk 0 0 0 19200000 0 0 50000 N
blsp1_uart2_apps_clk_src 0 0 0 19200000 0 0 50000 N
gcc_blsp1_uart2_apps_clk 0 0 0 19200000 0 0 50000 N
blsp1_uart1_apps_clk_src 0 0 0 19200000 0 0 50000 N
gcc_blsp1_uart1_apps_clk 0 0 0 19200000 0 0 50000 N
gpll0_main 1 1 0 800000000 0 0 50000 Y
gpll0_out_main_div2 0 0 0 400000000 0 0 50000 Y
gpll0 7 7 0 800000000 0 0 50000 Y
pcie0_rchng_clk_src 1 1 0 100000000 0 0 50000 Y
gcc_pcie0_rchng_clk 1 1 0 100000000 0 0 50000 Y
crypto_clk_src 1 1 0 160000000 0 0 50000 Y
gcc_crypto_clk 1 1 0 160000000 0 0 50000 Y
nss_imem_clk_src 1 1 0 400000000 0 0 50000 Y
gcc_nss_imem_clk 1 1 0 400000000 0 0 50000 Y
system_noc_bfdcd_clk_src 2 2 0 266666666 0 0 50000 Y
system_noc_clk_src 1 1 0 266666666 0 0 50000 Y
gcc_nssnoc_snoc_clk 1 1 0 266666666 0 0 50000 Y
usb1_master_clk_src 0 0 0 133333333 0 0 50000 Y
gcc_usb1_master_clk 0 0 0 133333333 0 0 50000 N
gcc_sys_noc_usb1_axi_clk 0 0 0 133333333 0 0 50000 N
usb0_master_clk_src 0 0 0 133333333 0 0 50000 N
gcc_usb0_master_clk 0 0 0 133333333 0 0 50000 N
gcc_sys_noc_usb0_axi_clk 0 0 0 133333333 0 0 50000 N
pcie1_axi_clk_src 0 0 0 200000000 0 0 50000 N
gcc_sys_noc_pcie1_axi_clk 0 0 0 200000000 0 0 50000 N
gcc_pcie1_axi_s_clk 0 0 0 200000000 0 0 50000 N
gcc_pcie1_axi_m_clk 0 0 0 200000000 0 0 50000 N
pcie0_axi_clk_src 4 4 0 200000000 0 0 50000 Y
gcc_pcie0_axi_s_bridge_clk 1 1 0 200000000 0 0 50000 Y
gcc_sys_noc_pcie0_axi_clk 1 1 0 200000000 0 0 50000 Y
gcc_pcie0_axi_s_clk 1 1 0 200000000 0 0 50000 Y
gcc_pcie0_axi_m_clk 1 1 0 200000000 0 0 50000 Y
pcnoc_bfdcd_clk_src 2 2 0 100000000 0 0 50000 Y
pcnoc_clk_src 12 12 0 100000000 0 0 50000 Y
gcc_crypto_axi_clk 1 1 0 100000000 0 0 50000 Y
gcc_crypto_ahb_clk 1 2 0 100000000 0 0 50000 Y
gcc_uniphy2_ahb_clk 1 1 0 100000000 0 0 50000 Y
gcc_uniphy1_ahb_clk 1 1 0 100000000 0 0 50000 Y
gcc_uniphy0_ahb_clk 1 1 0 100000000 0 0 50000 Y
gcc_mdio_ahb_clk 2 2 0 100000000 0 0 50000 Y
gcc_cmn_12gpll_ahb_clk 1 1 0 100000000 0 0 50000 Y
gcc_nss_cfg_clk 0 0 0 100000000 0 0 50000 N
gcc_sdcc2_ahb_clk 0 0 0 100000000 0 0 50000 N
gcc_sdcc1_ahb_clk 0 0 0 100000000 0 0 50000 N
gcc_usb1_phy_cfg_ahb_clk 0 0 0 100000000 0 0 50000 N
gcc_usb0_phy_cfg_ahb_clk 0 0 0 100000000 0 0 50000 N
gcc_pcie1_ahb_clk 0 0 0 100000000 0 0 50000 N
gcc_pcie0_ahb_clk 1 1 0 100000000 0 0 50000 Y
gcc_qpic_clk 1 1 0 100000000 0 0 50000 Y
gcc_qpic_ahb_clk 1 2 0 100000000 0 0 50000 Y
gcc_prng_ahb_clk 1 1 0 100000000 0 0 50000 Y
gcc_blsp1_ahb_clk 3 4 0 100000000 0 0 50000 N
blsp1_uart5_apps_clk_src 1 1 0 3686400 0 0 50003 Y
gcc_blsp1_uart5_apps_clk 3 3 0 3686400 0 0 50000 Y
blsp1_qup6_spi_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup6_spi_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup6_i2c_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup6_i2c_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup5_spi_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup5_spi_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup5_i2c_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup5_i2c_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup4_spi_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup4_spi_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup4_i2c_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup4_i2c_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup3_spi_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup3_spi_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup3_i2c_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup3_i2c_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup2_spi_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup2_spi_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup2_i2c_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup2_i2c_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup1_spi_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup1_spi_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup1_i2c_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup1_i2c_apps_clk 0 0 0 50000000 0 0 50000 N
sleep_clk 2 2 0 32768 0 0 50000 Y
gcc_sleep_clk_src 1 1 0 32768 0 0 50000 Y
gcc_usb1_sleep_clk 0 0 0 32768 0 0 50000 N
gcc_usb0_sleep_clk 0 0 0 32768 0 0 50000 N
usb1_pipe_clk_src 0 0 0 0 0 0 50000 Y
gcc_usb1_pipe_clk 0 0 0 0 0 0 50000 N
usb0_pipe_clk_src 0 0 0 0 0 0 50000 Y
gcc_usb0_pipe_clk 0 0 0 0 0 0 50000 N
pcie1_pipe_clk_src 0 0 0 0 0 0 50000 Y
gcc_pcie1_pipe_clk 0 0 0 0 0 0 50000 N
1 Like
Buildbots now have ipq807x target, so on next commit they are gonna start building images for ipq807x as well.
As soon as first images are available, I will kill the custom feed completely.
Update, there is a build queued but its gonna take some time for it to be in line
18 Likes
Just asking for curiosity, do we need to change compat_version before switching to openwrt snapshots?
It can be forced if you are on compat 2.0 but then it needs to be changed to update further.
But please do not update directly if you are not on a single rootfs already.