Ansuel
November 11, 2020, 4:59pm
589
Ok fixed... the makefile ignore the provided gcc flags and use his own... It was using the wrong flags.
@robimarko any idea about the dts entry for the ess switch? (i think we need to steal / dump them from the stock firmware, could also be that they are equal for every device)
ess-switch@3a000000 {
pinctrl-0 = <&uniphy_pins>;
pinctrl-names = "default";
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
switch_lan_bmp = <0x30>; /* lan port bitmap */
switch_wan_bmp = <0x40>; /* wan port bitmap */
switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
switch_mac_mode1 = <0xff>; /* mac mode for uniphy instance1*/
switch_mac_mode2 = <0xd>; /* mac mode for uniphy instance2*/
bm_tick_mode = <0>; /* bm tick mode */
tm_tick_mode = <0>; /* tm tick mode */
port_scheduler_resource {
port@0 {
port_id = <0>;
ucast_queue = <0 143>;
mcast_queue = <256 271>;
l0sp = <0 35>;
l0cdrr = <0 47>;
l0edrr = <0 47>;
l1cdrr = <0 7>;
l1edrr = <0 7>;
};
port@1 {
port_id = <1>;
ucast_queue = <144 159>;
mcast_queue = <272 275>;
l0sp = <36 39>;
l0cdrr = <48 63>;
l0edrr = <48 63>;
l1cdrr = <8 11>;
l1edrr = <8 11>;
};
port@2 {
port_id = <2>;
ucast_queue = <160 175>;
mcast_queue = <276 279>;
l0sp = <40 43>;
l0cdrr = <64 79>;
l0edrr = <64 79>;
l1cdrr = <12 15>;
l1edrr = <12 15>;
};
port@3 {
port_id = <3>;
ucast_queue = <176 191>;
mcast_queue = <280 283>;
l0sp = <44 47>;
l0cdrr = <80 95>;
l0edrr = <80 95>;
l1cdrr = <16 19>;
l1edrr = <16 19>;
};
port@4 {
port_id = <4>;
ucast_queue = <192 207>;
mcast_queue = <284 287>;
l0sp = <48 51>;
l0cdrr = <96 111>;
l0edrr = <96 111>;
l1cdrr = <20 23>;
l1edrr = <20 23>;
};
port@5 {
port_id = <5>;
ucast_queue = <208 223>;
mcast_queue = <288 291>;
l0sp = <52 55>;
l0cdrr = <112 127>;
l0edrr = <112 127>;
l1cdrr = <24 27>;
l1edrr = <24 27>;
};
port@6 {
port_id = <6>;
ucast_queue = <224 239>;
mcast_queue = <292 295>;
l0sp = <56 59>;
l0cdrr = <128 143>;
l0edrr = <128 143>;
l1cdrr = <28 31>;
l1edrr = <28 31>;
};
port@7 {
port_id = <7>;
ucast_queue = <240 255>;
mcast_queue = <296 299>;
l0sp = <60 63>;
l0cdrr = <144 159>;
l0edrr = <144 159>;
l1cdrr = <32 35>;
l1edrr = <32 35>;
};
};
port_scheduler_config {
port@0 {
port_id = <0>;
l1scheduler {
group@0 {
sp = <0 1>; /*L0 SPs*/
/*cpri cdrr epri edrr*/
cfg = <0 0 0 0>;
};
};
l0scheduler {
group@0 {
/*unicast queues*/
ucast_queue = <0 4 8>;
/*multicast queues*/
mcast_queue = <256 260>;
/*sp cpri cdrr epri edrr*/
cfg = <0 0 0 0 0>;
};
group@1 {
ucast_queue = <1 5 9>;
mcast_queue = <257 261>;
cfg = <0 1 1 1 1>;
};
group@2 {
ucast_queue = <2 6 10>;
mcast_queue = <258 262>;
cfg = <0 2 2 2 2>;
};
group@3 {
ucast_queue = <3 7 11>;
mcast_queue = <259 263>;
cfg = <0 3 3 3 3>;
};
};
};
port@1 {
port_id = <1>;
l1scheduler {
group@0 {
sp = <36>;
cfg = <0 8 0 8>;
};
group@1 {
sp = <37>;
cfg = <1 9 1 9>;
};
};
l0scheduler {
group@0 {
ucast_queue = <144>;
ucast_loop_pri = <16>;
mcast_queue = <272>;
mcast_loop_pri = <4>;
cfg = <36 0 48 0 48>;
};
};
};
port@2 {
port_id = <2>;
l1scheduler {
group@0 {
sp = <40>;
cfg = <0 12 0 12>;
};
group@1 {
sp = <41>;
cfg = <1 13 1 13>;
};
};
l0scheduler {
group@0 {
ucast_queue = <160>;
ucast_loop_pri = <16>;
mcast_queue = <276>;
mcast_loop_pri = <4>;
cfg = <40 0 64 0 64>;
};
};
};
port@3 {
port_id = <3>;
l1scheduler {
group@0 {
sp = <44>;
cfg = <0 16 0 16>;
};
group@1 {
sp = <45>;
cfg = <1 17 1 17>;
};
};
l0scheduler {
group@0 {
ucast_queue = <176>;
ucast_loop_pri = <16>;
mcast_queue = <280>;
mcast_loop_pri = <4>;
cfg = <44 0 80 0 80>;
};
};
};
port@4 {
port_id = <4>;
l1scheduler {
group@0 {
sp = <48>;
cfg = <0 20 0 20>;
};
group@1 {
sp = <49>;
cfg = <1 21 1 21>;
};
};
l0scheduler {
group@0 {
ucast_queue = <192>;
ucast_loop_pri = <16>;
mcast_queue = <284>;
mcast_loop_pri = <4>;
cfg = <48 0 96 0 96>;
};
};
};
port@5 {
port_id = <5>;
l1scheduler {
group@0 {
sp = <52>;
cfg = <0 24 0 24>;
};
group@1 {
sp = <53>;
cfg = <1 25 1 25>;
};
};
l0scheduler {
group@0 {
ucast_queue = <208>;
ucast_loop_pri = <16>;
mcast_queue = <288>;
mcast_loop_pri = <4>;
cfg = <52 0 112 0 112>;
};
};
};
port@6 {
port_id = <6>;
l1scheduler {
group@0 {
sp = <56>;
cfg = <0 28 0 28>;
};
group@1 {
sp = <57>;
cfg = <1 29 1 29>;
};
};
l0scheduler {
group@0 {
ucast_queue = <224>;
ucast_loop_pri = <16>;
mcast_queue = <292>;
mcast_loop_pri = <4>;
cfg = <56 0 128 0 128>;
};
};
};
port@7 {
port_id = <7>;
l1scheduler {
group@0 {
sp = <60>;
cfg = <0 32 0 32>;
};
group@1 {
sp = <61>;
cfg = <1 33 1 33>;
};
};
l0scheduler {
group@0 {
ucast_queue = <240>;
ucast_loop_pri = <16>;
mcast_queue = <296>;
cfg = <60 0 144 0 144>;
};
};
};
};
};
https://pastebin.com/raw/b6kMeYma < DTS from stock (non worldwide) FW
Seems it was removed moments after i posted it ....... safe to post on here ?
Ansuel
November 11, 2020, 5:13pm
593
imho yes... nothing special in it and can be extracted in some way from the firmware so.... ?
Ansuel
November 11, 2020, 5:18pm
595
ok quick check and ess conf looks the same... so i can assume without any proof that it's the same for every ipq807x target LOL (7 port conf with a device that has 4 port...)
wouldn't surprise me, there are very few modifications in comparison to the AC04 board.
I think UBOOT also think the full set of ethernet ports are available (but LINK down)
Ansuel
November 11, 2020, 5:25pm
597
(wonder if they just didn't populate the port on the pcb or just a bug or they don't have a way to check if the port really exist or not)
They probably just got the AC01 and chopped of components (usb ect) and called it a day.
At least there is no unpopulated ethernet ports on the PCB
QCA8075 PHY has 5 ports as well as the switch.
Ansuel
November 11, 2020, 5:33pm
600
Wonder if tftpboot works. Did anyone tested that?
Yeah that's how IV been developing things on the unit
See Adding OpenWrt support for Xiaomi AX3600
1 Like
Thats all I have been using
Ansuel
November 11, 2020, 7:16pm
603
A good start! (quick fix they, in the driver they hardcode the mdio compatible and the name changed in upstream)
[ 6.049193] ssdk_switch_device_num_init[1090]:INFO:
[ 6.049197] ess-switch dts node number: 1
[ 6.061717] ssdk_dt_get_switch_node[923]:INFO:
[ 6.061719] ess-switch DT exist!
[ 6.070162] ssdk_dt_parse_access_mode[824]:INFO:
[ 6.070164] switch_access_mode: local bus
[ 6.078142] ssdk_dt_parse_access_mode[837]:INFO:
[ 6.078145] switchreg_base_addr: 0x3a000000
[ 6.086735] ssdk_dt_parse_access_mode[838]:INFO:
[ 6.086738] switchreg_size: 0x1000000
[ 6.095503] ssdk_dt_parse_mac_mode[288]:INFO:
[ 6.095505] mac mode = 0x0
[ 6.103400] ssdk_dt_parse_mac_mode[297]:INFO:
[ 6.103403] mac mode1 = 0xff
[ 6.110433] ssdk_dt_parse_mac_mode[306]:INFO:
[ 6.110435] mac mode2 = 0xff
[ 6.117691] ssdk_dt_parse_uniphy[325]:INFO:
[ 6.117692] ess-uniphy DT exist!
[ 6.124904] ssdk_plat_init start
[ 6.128063] miibus_get[572]:ERROR:
[ 6.128064] No MDIO node found in DTS!
[ 6.134429] regi_init[3455]:INFO:
[ 6.134432] qca-ssdk module init, no device found!
[ 6.028184] ssdk_switch_device_num_init[1090]:INFO:
[ 6.028188] ess-switch dts node number: 1
[ 6.036185] ssdk_dt_get_switch_node[923]:INFO:
[ 6.036187] ess-switch DT exist!
[ 6.044630] ssdk_dt_parse_access_mode[824]:INFO:
[ 6.044632] switch_access_mode: local bus
[ 6.052612] ssdk_dt_parse_access_mode[837]:INFO:
[ 6.052615] switchreg_base_addr: 0x3a000000
[ 6.061204] ssdk_dt_parse_access_mode[838]:INFO:
[ 6.061207] switchreg_size: 0x1000000
[ 6.069973] ssdk_dt_parse_mac_mode[288]:INFO:
[ 6.069976] mac mode = 0x0
[ 6.077870] ssdk_dt_parse_mac_mode[297]:INFO:
[ 6.077872] mac mode1 = 0xff
[ 6.084902] ssdk_dt_parse_mac_mode[306]:INFO:
[ 6.084904] mac mode2 = 0xff
[ 6.092161] ssdk_dt_parse_uniphy[325]:INFO:
[ 6.092163] ess-uniphy DT exist!
[ 6.099374] ssdk_plat_init start
[ 6.103568] ------------[ cut here ]------------
[ 6.105648] nss_crypto_pll_main failed to enable!
[ 6.110279] WARNING: CPU: 3 PID: 1004 at wait_for_pll+0xc4/0xd0
[ 6.114850] Modules linked in: qca_ssdk(+) michael_mic crypto_acompress usb_storage leds_gpio dwc3 ahci libahci libata sd_mod scsi_mod gpio_button_hotplug ext4 mbcache jbd2 btrfs xor zstd_decompress zstd_compress zlib_inflate zlib_deflate xxhash xor_neon raid6_pq lzo_decompress lzo_compress libcrc32c usbcore nls_base usb_common crc16 crc32c_generic
[ 6.129251] CPU: 3 PID: 1004 Comm: kmodloader Tainted: G W 5.9.6 #0
[ 6.151486] Hardware name: Xiaomi Mi AIoT Router AX3600 (DT)
[ 6.159038] pstate: 60400085 (nZCv daIf +PAN -UAO BTYPE=--)
[ 6.164852] pc : wait_for_pll+0xc4/0xd0
[ 6.170142] lr : wait_for_pll+0xc4/0xd0
[ 6.173960] sp : ffffffc012bc3720
[ 6.177780] x29: ffffffc012bc3720 x28: ffffffc01009e980
[ 6.181255] x27: 0000000000000001 x26: 0000000000000000
[ 6.186638] x25: ffffff8002ecf700 x24: 0000000000000000
[ 6.191932] x23: ffffffc010733ff8 x22: ffffffc010715710
[ 6.197227] x21: 0000000000000000 x20: 0000000080000000
[ 6.202523] x19: ffffffc0122230f0 x18: 0000000000000030
[ 6.207817] x17: 0000000000000000 x16: 0000000000000000
[ 6.213113] x15: ffffff801ea95e08 x14: 0000000000000005
[ 6.218408] x13: ffffffc092bc3467 x12: ffffffc012bc346f
[ 6.223704] x11: 0000000000000004 x10: 000000000000000d
[ 6.228998] x9 : ffffffc012bc347c x8 : 0000000000000001
[ 6.234293] x7 : 0000000000000000 x6 : 0000000000000139
[ 6.239588] x5 : 0000000000000036 x4 : 0000000000000000
[ 6.244883] x3 : 0000000000000000 x2 : 00000000ffffffff
[ 6.250179] x1 : ffffffc012205fb0 x0 : 0000000000000025
[ 6.255475] Call trace:
[ 6.260765] wait_for_pll+0xc4/0xd0
[ 6.262938] clk_alpha_pll_enable+0xe4/0x110
[ 6.266413] clk_core_enable+0x6c/0xc0
[ 6.270924] clk_core_enable+0x50/0xc0
[ 6.274482] clk_core_enable+0x50/0xc0
[ 6.278216] clk_core_enable+0x50/0xc0
[ 6.281949] clk_enable+0x28/0x54
[ 6.286425] shiva_vlan_init+0x2f0/0x558 [qca_ssdk]
[ 6.289746] ssdk_clock_rate_set_and_enable+0x2f8/0x480 [qca_ssdk]
[ 6.294412] ssdk_gcc_clock_init+0xcc/0x208 [qca_ssdk]
[ 6.300660] ssdk_plat_init+0x398/0x510 [qca_ssdk]
[ 6.305770] init_module+0x278/0x2000 [qca_ssdk]
[ 6.309906] do_one_initcall+0x54/0x1bc
[ 6.314676] do_init_module+0x54/0x1e0
[ 6.318233] load_module+0x1b70/0x2194
[ 6.322052] __do_sys_init_module+0x17c/0x270
[ 6.325787] __arm64_sys_init_module+0x1c/0x30
[ 6.330217] do_el0_svc+0x90/0x140
[ 6.334553] el0_sync_handler+0x98/0x2b8
[ 6.337938] el0_sync+0x15c/0x180
[ 6.342016] ---[ end trace 8c41a3c41c0aee81 ]---
[ 6.408940] ssdk_gcc_clock_init[1119]:INFO:
[ 6.408944] SSDK gcc clock init successfully!
[ 6.412095] ssdk_probe[1950]:INFO:
[ 6.412097] ess_rst doesn't exist!
[ 6.420690] HPPE initializing...
[ 6.423409] malibu_phy_api_ops_init[2849]:INFO:
[ 6.423414] qca probe malibu phy driver succeeded!
[ 6.436736] regi_init[3396]:INFO:
[ 6.436740] Initializing HPPE!!
[ 6.654860] ssdk_ppe_reset_init[1350]:INFO:
[ 6.654864] ppe reset successfully!
[ 6.661160] qca_hppe_tdm_hw_init[674]:INFO:
[ 6.661163] tdm setup num=96
[ 6.665818] qca_hppe_portctrl_hw_init[105]:INFO:
[ 6.665820] Hawkeye PPE port initializing
[ 6.886385] ssdk_switch_register[1651]:INFO:
[ 6.886389] Chip version 0x1500
[ 6.889729] qca_link_polling_select[1285]:INFO:
[ 6.889731] link-polling-required node does not exist
[ 6.897095] ssdk_switch_register[1676]:INFO:
[ 6.897097] polling is selected
[ 6.906645] regi_init[3400]:INFO:
[ 6.906647] Initializing HPPE Done!!
[ 6.913055] regi_init[3451]:INFO:
[ 6.913058] qca-ssdk module init succeeded!
done
next task is port the dp driver and we should have ethernet... problem is that for now ssdk driver is compiled without swconfig support... does dp driver needs swconfig?
2 Likes
Yeah, I remember that once trying to port it before.
Nice job, you ported the NSS DP as well?
Ansuel
November 11, 2020, 7:38pm
605
nope... did you read the swconfig part?
juppin
November 11, 2020, 7:45pm
606
I'm right that this ssdk stuff would never go mainline to OpenWrt?
Ansuel
November 11, 2020, 7:46pm
607
NEVER. too much shit in one driver... a dedicated driver is needed 100% the relevant part is the init part of the driver (the driver is split in various dir and the init dir is the important dir)
1 Like
Not really, its been extremely busy week so far and I have been able to only glimpse through this
