Considering there is no offloading you are not gonna get close to stock FW
1 Like
can you share the output of ethtool 10g-2 (I presume this is the port that is bridged to br-lan and that you used to connect to your asus 10g nic)?
second point - i can see the load mostly on cpu0 ... try irqbalance or/and otherwise move some of the interrupts to the other cpu's ...
on 2 1g ports (i am using mwan3) I get the 1.2Mb so surprised as you you are not getting more even without HW offloading...
Ping: 17 ms.
Jitter: 8 ms.
Determine line type (2) ........................
Fiber / Lan line type detected: profile selected fiber
Testing download speed (32) ................................................................................................................................................................................................................................................................................................................................
Download: 1211.70 Mbit/s
Testing upload speed (12) ....................................................................................
Upload: 54.50 Mbit/s
alternatively you could try adding to your own build the qca-nss-drv that brings some optimisations without HW offloading (NSS-ECM). My personal tests with NSS-ECM haven't shown noticeable improvements though but this is most likely to do with my own use case
root@OpenWrt:~# ethtool 10g-2
Settings for 10g-2:
Supported ports: [ ]
Supported link modes: 100baseT/Half 100baseT/Full
1000baseT/Full
10000baseT/Full
1000baseKX/Full
10000baseKX4/Full
10000baseKR/Full
2500baseT/Full
5000baseT/Full
Supported pause frame use: Symmetric Receive-only
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 100baseT/Half 100baseT/Full
1000baseT/Full
10000baseT/Full
1000baseKX/Full
10000baseKX4/Full
10000baseKR/Full
Advertised pause frame use: Symmetric Receive-only
Advertised auto-negotiation: Yes
Advertised FEC modes: Not reported
Link partner advertised link modes: 100baseT/Full
1000baseT/Full
10000baseT/Full
2500baseT/Full
5000baseT/Full
Link partner advertised pause frame use: No
Link partner advertised auto-negotiation: Yes
Link partner advertised FEC modes: Not reported
Speed: 10000Mb/s
Duplex: Full
Auto-negotiation: on
Port: Twisted Pair
PHYAD: 0
Transceiver: external
MDI-X: Unknown
Link detected: yes
irqbalance enabled and not working. I'll look into NSS-ECM.
root@OpenWrt:~# speedtest-netperf.sh -H netperf-west.bufferbloat.net
2023-01-11 02:41:56 Starting speedtest for 60 seconds per transfer session.
Measure speed to netperf-west.bufferbloat.net (IPv4) while pinging gstatic.com.
Download and upload sessions are sequential, each with 5 simultaneous streams.
............................................................
Download: 2100.57 Mbps
Latency: [in msec, 0 pings, 0.00% packet loss]
CPU Load: [in % busy (avg +/- std dev) @ avg frequency, 57 samples]
cpu0: 97.4 +/- 0.0 @ 2203 MHz
cpu1: 19.0 +/- 1.7 @ 2198 MHz
cpu2: 20.1 +/- 2.2 @ 2203 MHz
cpu3: 18.3 +/- 2.4 @ 2198 MHz
Overhead: [in % used of total CPU available]
netperf: 13.9
............................................................
Upload: 1371.50 Mbps
Latency: [in msec, 0 pings, 0.00% packet loss]
CPU Load: [in % busy (avg +/- std dev) @ avg frequency, 57 samples]
cpu0: 36.2 +/- 4.1 @ 1361 MHz
cpu1: 31.3 +/- 5.4 @ 1428 MHz
cpu2: 16.9 +/- 3.8 @ 1437 MHz
cpu3: 14.5 +/- 3.5 @ 1526 MHz
Overhead: [in % used of total CPU available]
netperf: 8.7
No, I am still stuck at <400mbit/s to WAN, even though my local link rates are ~2gbit/s. Unsure what it is with this device.
That is crazy low, even with PPoE you should be getting 800+ with NAT
Running a wan speed test on the qnap itself yields pretty close to the expected speeds, but any devices connected to it are capped. Not a super crazy config; mostly just straight NAT.
It seems to derive from advertising 2.5G on 10g wan with
ethtool -s 10g-2 advertise 18000000E102C
ethtool -s 10g-1 advertise 18000000E102C
Hm, that is really, really weird.
Can you dump the clocks with:
cat /sys/kernel/debug/clk/clk_summary
Not sure why my post above was flagged but I have all my speed problem fixed with a build from some chinese developers. Looks like they have the flow offloading working. Full 8000 mbit/s when testing from computer.
Advertising random chinese builds as the solution isn't really well-liked as that is not OpenWrt
3 Likes
Can you please post the more information on the other build? Is it on github?
Also looking at the screenshots and doing some googling, looks like we just need qca-nss-ecm added to the firmware which appears to be on github and in some other openwrt builds already. I could be wrong but looks promising.
"Just" is a bit of an understatement
I assume that is isn't easy like adding software in the firmware under the software tab?
The build itself no, but it was forked off of this build: https://github.com/coolsnowwolf/lede
The builds are here: https://drive.google.com/drive/folders/19q9ZXNvUXArASm21ntiPbo1a_pmQByRj
Not really, as that broken junk requires a bit less broken, but still broken junk called NSS-DRV
cat /sys/kernel/debug/clk/clk_summary
enable prepare protect duty hardware
clock count count count rate accuracy phase cycle enable
-------------------------------------------------------------------------------------------------------
uniphy2_gcc_tx_clk 1 1 0 312500000 0 0 50000 Y
nss_port6_tx_clk_src 1 1 0 312500000 0 0 50000 Y
nss_port6_tx_div_clk_src 2 2 0 312500000 0 0 50000 Y
gcc_uniphy2_port6_tx_clk 1 1 0 312500000 0 0 50000 Y
gcc_nss_port6_tx_clk 1 1 0 312500000 0 0 50000 Y
uniphy2_gcc_rx_clk 1 1 0 312500000 0 0 50000 Y
nss_port6_rx_clk_src 1 1 0 312500000 0 0 50000 Y
nss_port6_rx_div_clk_src 2 2 0 312500000 0 0 50000 Y
gcc_uniphy2_port6_rx_clk 1 1 0 312500000 0 0 50000 Y
gcc_nss_port6_rx_clk 1 1 0 312500000 0 0 50000 Y
uniphy1_gcc_tx_clk 1 1 0 312500000 0 0 50000 Y
nss_port5_tx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port5_tx_div_clk_src 3 3 0 125000000 0 0 50000 Y
gcc_uniphy1_port5_tx_clk 1 1 0 125000000 0 0 50000 Y
gcc_uniphy0_port5_tx_clk 1 1 0 125000000 0 0 50000 Y
gcc_nss_port5_tx_clk 1 1 0 125000000 0 0 50000 Y
uniphy1_gcc_rx_clk 1 1 0 312500000 0 0 50000 Y
nss_port5_rx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port5_rx_div_clk_src 3 3 0 125000000 0 0 50000 Y
gcc_uniphy1_port5_rx_clk 1 1 0 125000000 0 0 50000 Y
gcc_uniphy0_port5_rx_clk 1 1 0 125000000 0 0 50000 Y
gcc_nss_port5_rx_clk 1 1 0 125000000 0 0 50000 Y
uniphy0_gcc_tx_clk 4 4 0 125000000 0 0 50000 Y
nss_port1_tx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port1_tx_div_clk_src 2 2 0 25000000 0 0 50000 Y
gcc_uniphy0_port1_tx_clk 1 1 0 25000000 0 0 50000 Y
gcc_nss_port1_tx_clk 1 1 0 25000000 0 0 50000 Y
nss_port2_tx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port2_tx_div_clk_src 2 2 0 125000000 0 0 50000 Y
gcc_uniphy0_port2_tx_clk 1 1 0 125000000 0 0 50000 Y
gcc_nss_port2_tx_clk 1 1 0 125000000 0 0 50000 Y
nss_port3_tx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port3_tx_div_clk_src 2 2 0 125000000 0 0 50000 Y
gcc_uniphy0_port3_tx_clk 1 1 0 125000000 0 0 50000 Y
gcc_nss_port3_tx_clk 1 1 0 125000000 0 0 50000 Y
nss_port4_tx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port4_tx_div_clk_src 2 2 0 125000000 0 0 50000 Y
gcc_uniphy0_port4_tx_clk 1 1 0 125000000 0 0 50000 Y
gcc_nss_port4_tx_clk 1 1 0 125000000 0 0 50000 Y
uniphy0_gcc_rx_clk 4 4 0 125000000 0 0 50000 Y
nss_port1_rx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port1_rx_div_clk_src 2 2 0 25000000 0 0 50000 Y
gcc_uniphy0_port1_rx_clk 1 1 0 25000000 0 0 50000 Y
gcc_nss_port1_rx_clk 1 1 0 25000000 0 0 50000 Y
nss_port2_rx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port2_rx_div_clk_src 2 2 0 125000000 0 0 50000 Y
gcc_uniphy0_port2_rx_clk 1 1 0 125000000 0 0 50000 Y
gcc_nss_port2_rx_clk 1 1 0 125000000 0 0 50000 Y
nss_port3_rx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port3_rx_div_clk_src 2 2 0 125000000 0 0 50000 Y
gcc_uniphy0_port3_rx_clk 1 1 0 125000000 0 0 50000 Y
gcc_nss_port3_rx_clk 1 1 0 125000000 0 0 50000 Y
nss_port4_rx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port4_rx_div_clk_src 2 2 0 125000000 0 0 50000 Y
gcc_uniphy0_port4_rx_clk 1 1 0 125000000 0 0 50000 Y
gcc_nss_port4_rx_clk 1 1 0 125000000 0 0 50000 Y
usb3phy_0_cc_pipe_clk 1 1 0 125000000 0 0 50000 Y
usb0_pipe_clk_src 1 1 0 125000000 0 0 50000 Y
gcc_usb0_pipe_clk 1 1 0 125000000 0 0 50000 Y
usb3phy_1_cc_pipe_clk 1 1 0 125000000 0 0 50000 Y
usb1_pipe_clk_src 1 1 0 125000000 0 0 50000 Y
gcc_usb1_pipe_clk 1 1 0 125000000 0 0 50000 Y
bias_pll_nss_noc_clk 1 1 0 416500000 0 0 50000 Y
nss_noc_bfdcd_clk_src 1 1 0 416500000 0 0 50000 Y
nss_noc_clk_src 2 2 0 416500000 0 0 50000 Y
gcc_ubi1_nc_axi_clk 0 0 0 416500000 0 0 50000 N
gcc_ubi1_axi_clk 0 0 0 416500000 0 0 50000 N
gcc_ubi0_nc_axi_clk 0 0 0 416500000 0 0 50000 N
gcc_ubi0_axi_clk 0 0 0 416500000 0 0 50000 N
gcc_nss_noc_clk 1 1 0 416500000 0 0 50000 Y
gcc_mem_noc_nss_axi_clk 1 1 0 416500000 0 0 50000 Y
bias_pll_cc_clk 1 1 0 300000000 0 0 50000 Y
nss_ppe_clk_src 15 15 0 300000000 0 0 50000 Y
gcc_crypto_ppe_clk 0 0 0 300000000 0 0 50000 N
gcc_port6_mac_clk 1 1 0 300000000 0 0 50000 Y
gcc_port5_mac_clk 1 1 0 300000000 0 0 50000 Y
gcc_port4_mac_clk 1 1 0 300000000 0 0 50000 Y
gcc_port3_mac_clk 1 1 0 300000000 0 0 50000 Y
gcc_port2_mac_clk 1 1 0 300000000 0 0 50000 Y
gcc_port1_mac_clk 1 1 0 300000000 0 0 50000 Y
gcc_nssnoc_ppe_clk 1 1 0 300000000 0 0 50000 Y
gcc_nssnoc_ppe_cfg_clk 1 1 0 300000000 0 0 50000 Y
gcc_nss_ppe_ipe_clk 1 1 0 300000000 0 0 50000 Y
gcc_nss_ppe_clk 1 1 0 300000000 0 0 50000 Y
gcc_nss_ppe_cfg_clk 1 1 0 300000000 0 0 50000 Y
gcc_nss_ppe_btq_clk 1 1 0 300000000 0 0 50000 Y
gcc_nss_edma_clk 1 1 0 300000000 0 0 50000 Y
gcc_nss_edma_cfg_clk 1 1 0 300000000 0 0 50000 Y
nss_ppe_cdiv_clk_src 1 1 0 75000000 0 0 50000 Y
gcc_nss_ptp_ref_clk 1 1 0 75000000 0 0 50000 Y
xo 13 13 0 19200000 0 0 50000 Y
usb1_mock_utmi_clk_src 1 1 0 19200000 0 0 55555 Y
gcc_usb1_mock_utmi_clk 1 1 0 19200000 0 0 50000 Y
usb0_mock_utmi_clk_src 1 1 0 19200000 0 0 55555 Y
gcc_usb0_mock_utmi_clk 1 1 0 19200000 0 0 50000 Y
a53pll 1 1 0 1382400000 0 0 50000 Y
apcs_alias0_clk_src 1 1 0 1382400000 0 0 50000 Y
apcs_alias0_core_clk 1 1 0 1382400000 0 0 50000 Y
pcie0_rchng_clk_src 0 0 0 19200000 0 0 50000 N
gcc_pcie0_rchng_clk 0 0 0 19200000 0 0 50000 N
gp3_clk_src 0 0 0 19200000 0 0 50000 N
gcc_gp3_clk 0 0 0 19200000 0 0 50000 N
gp2_clk_src 0 0 0 19200000 0 0 50000 N
gcc_gp2_clk 0 0 0 19200000 0 0 50000 N
gp1_clk_src 0 0 0 19200000 0 0 50000 N
gcc_gp1_clk 0 0 0 19200000 0 0 50000 N
ubi_mpt_clk_src 0 0 0 19200000 0 0 50000 N
gcc_ubi1_mpt_clk 0 0 0 19200000 0 0 50000 N
gcc_ubi0_mpt_clk 0 0 0 19200000 0 0 50000 N
nss_ubi1_clk_src 0 0 0 19200000 0 0 50000 N
nss_ubi1_div_clk_src 0 0 0 19200000 0 0 50000 Y
gcc_ubi1_core_clk 0 0 0 19200000 0 0 50000 N
nss_ubi0_clk_src 0 0 0 19200000 0 0 50000 N
nss_ubi0_div_clk_src 0 0 0 19200000 0 0 50000 Y
gcc_ubi0_core_clk 0 0 0 19200000 0 0 50000 N
nss_ce_clk_src 0 0 0 19200000 0 0 50000 N
gcc_ubi1_ahb_clk 0 0 0 19200000 0 0 50000 N
gcc_ubi0_ahb_clk 0 0 0 19200000 0 0 50000 N
gcc_nssnoc_ubi1_ahb_clk 0 0 0 19200000 0 0 50000 N
gcc_nssnoc_ubi0_ahb_clk 0 0 0 19200000 0 0 50000 N
gcc_nssnoc_ce_axi_clk 0 0 0 19200000 0 0 50000 N
gcc_nssnoc_ce_apb_clk 0 0 0 19200000 0 0 50000 N
gcc_nss_csr_clk 0 0 0 19200000 0 0 50000 N
gcc_nss_ce_axi_clk 0 0 0 19200000 0 0 50000 N
gcc_nss_ce_apb_clk 0 0 0 19200000 0 0 50000 N
gcc_xo_clk_src 5 5 0 19200000 0 0 50000 Y
gcc_uniphy2_sys_clk 1 1 0 19200000 0 0 50000 Y
gcc_uniphy1_sys_clk 1 1 0 19200000 0 0 50000 Y
gcc_uniphy0_sys_clk 1 1 0 19200000 0 0 50000 Y
gcc_cmn_12gpll_sys_clk 1 1 0 19200000 0 0 50000 Y
gcc_nssnoc_qosgen_ref_clk 0 0 0 19200000 0 0 50000 N
gcc_xo_div4_clk_src 0 0 0 4800000 0 0 50000 Y
gcc_nssnoc_timeout_ref_clk 0 0 0 4800000 0 0 50000 N
usb1_aux_clk_src 1 1 0 19200000 0 0 50000 Y
gcc_usb1_aux_clk 1 1 0 19200000 0 0 50000 Y
usb0_aux_clk_src 1 1 0 19200000 0 0 50000 Y
gcc_usb0_aux_clk 1 1 0 19200000 0 0 50000 Y
sdcc2_apps_clk_src 0 0 0 19200000 0 0 50000 N
gcc_sdcc2_apps_clk 0 0 0 19200000 0 0 50000 N
pcie1_aux_clk_src 0 0 0 19200000 0 0 50000 N
gcc_pcie1_aux_clk 0 0 0 19200000 0 0 50000 N
pcie1_axi_clk_src 0 0 0 19200000 0 0 50000 N
gcc_sys_noc_pcie1_axi_clk 0 0 0 19200000 0 0 50000 N
gcc_pcie1_axi_s_clk 0 0 0 19200000 0 0 50000 N
gcc_pcie1_axi_m_clk 0 0 0 19200000 0 0 50000 N
pcie0_aux_clk_src 0 0 0 19200000 0 0 50000 Y
gcc_pcie0_aux_clk 0 0 0 19200000 0 0 50000 N
pcie0_axi_clk_src 0 0 0 19200000 0 0 50000 Y
gcc_pcie0_axi_s_bridge_clk 0 0 0 19200000 0 0 50000 N
gcc_sys_noc_pcie0_axi_clk 0 0 0 19200000 0 0 50000 N
gcc_pcie0_axi_s_clk 0 0 0 19200000 0 0 50000 N
gcc_pcie0_axi_m_clk 0 0 0 19200000 0 0 50000 N
nss_crypto_pll_main 1 1 0 1190400000 0 0 50000 Y
nss_crypto_pll 1 1 0 595200000 0 0 50000 Y
nss_crypto_clk_src 1 1 0 595200000 0 0 50000 Y
gcc_nssnoc_crypto_clk 0 0 0 595200000 0 0 50000 N
gcc_nss_crypto_clk 1 1 0 595200000 0 0 50000 Y
ubi32_pll_main 0 0 0 1497600000 0 0 50000 N
ubi32_pll 0 0 0 1497600000 0 0 50000 Y
gpll6_main 1 1 0 1080000000 0 0 50000 Y
gpll6 0 0 0 1080000000 0 0 50000 Y
sdcc1_ice_core_clk_src 0 0 0 308571428 0 0 50000 N
gcc_sdcc1_ice_core_clk 0 0 0 308571428 0 0 50000 N
gpll6_out_main_div2 0 0 0 540000000 0 0 50000 Y
gpll4_main 1 1 0 1200000000 0 0 50000 Y
gpll4 0 0 0 1200000000 0 0 50000 Y
gpll2_main 1 1 0 1152000000 0 0 50000 Y
gpll2 0 0 0 1152000000 0 0 50000 Y
sdcc1_apps_clk_src 0 0 0 192000000 0 0 50000 N
gcc_sdcc1_apps_clk 0 0 0 192000000 0 0 50000 N
blsp1_uart6_apps_clk_src 0 0 0 19200000 0 0 50000 N
gcc_blsp1_uart6_apps_clk 0 0 0 19200000 0 0 50000 N
blsp1_uart4_apps_clk_src 0 0 0 19200000 0 0 50000 N
gcc_blsp1_uart4_apps_clk 0 0 0 19200000 0 0 50000 N
blsp1_uart3_apps_clk_src 0 0 0 19200000 0 0 50000 N
gcc_blsp1_uart3_apps_clk 0 0 0 19200000 0 0 50000 N
blsp1_uart2_apps_clk_src 0 0 0 19200000 0 0 50000 N
gcc_blsp1_uart2_apps_clk 0 0 0 19200000 0 0 50000 N
blsp1_uart1_apps_clk_src 0 0 0 19200000 0 0 50000 N
gcc_blsp1_uart1_apps_clk 0 0 0 19200000 0 0 50000 N
gpll0_main 1 1 0 800000000 0 0 50000 Y
gpll0_out_main_div2 0 0 0 400000000 0 0 50000 Y
gpll0 7 7 0 800000000 0 0 50000 Y
crypto_clk_src 1 1 0 160000000 0 0 50000 Y
gcc_crypto_clk 1 1 0 160000000 0 0 50000 Y
nss_imem_clk_src 1 1 0 400000000 0 0 50000 Y
gcc_nss_imem_clk 1 1 0 400000000 0 0 50000 Y
system_noc_bfdcd_clk_src 2 2 0 266666666 0 0 50000 Y
system_noc_clk_src 1 1 0 266666666 0 0 50000 Y
gcc_nssnoc_snoc_clk 1 1 0 266666666 0 0 50000 Y
usb1_master_clk_src 2 2 0 133333333 0 0 50000 Y
gcc_usb1_master_clk 1 1 0 133333333 0 0 50000 Y
gcc_sys_noc_usb1_axi_clk 1 1 0 133333333 0 0 50000 Y
usb0_master_clk_src 2 2 0 133333333 0 0 50000 Y
gcc_usb0_master_clk 1 1 0 133333333 0 0 50000 Y
gcc_sys_noc_usb0_axi_clk 1 1 0 133333333 0 0 50000 Y
pcnoc_bfdcd_clk_src 2 2 0 100000000 0 0 50000 Y
pcnoc_clk_src 11 12 0 100000000 0 0 50000 Y
gcc_crypto_axi_clk 1 1 0 100000000 0 0 50000 Y
gcc_crypto_ahb_clk 1 2 0 100000000 0 0 50000 Y
gcc_uniphy2_ahb_clk 1 1 0 100000000 0 0 50000 Y
gcc_uniphy1_ahb_clk 1 1 0 100000000 0 0 50000 Y
gcc_uniphy0_ahb_clk 1 1 0 100000000 0 0 50000 Y
gcc_mdio_ahb_clk 2 2 0 100000000 0 0 50000 Y
gcc_cmn_12gpll_ahb_clk 1 1 0 100000000 0 0 50000 Y
gcc_nss_cfg_clk 0 0 0 100000000 0 0 50000 N
gcc_sdcc2_ahb_clk 0 0 0 100000000 0 0 50000 N
gcc_sdcc1_ahb_clk 0 0 0 100000000 0 0 50000 N
gcc_usb1_phy_cfg_ahb_clk 2 2 0 100000000 0 0 50000 Y
gcc_usb0_phy_cfg_ahb_clk 2 2 0 100000000 0 0 50000 Y
gcc_pcie1_ahb_clk 0 0 0 100000000 0 0 50000 N
gcc_pcie0_ahb_clk 0 0 0 100000000 0 0 50000 N
gcc_qpic_clk 0 0 0 100000000 0 0 50000 N
gcc_qpic_ahb_clk 0 1 0 100000000 0 0 50000 N
gcc_prng_ahb_clk 1 1 0 100000000 0 0 50000 Y
gcc_blsp1_ahb_clk 3 4 0 100000000 0 0 50000 N
blsp1_uart5_apps_clk_src 1 1 0 3686400 0 0 50003 Y
gcc_blsp1_uart5_apps_clk 3 3 0 3686400 0 0 50000 Y
blsp1_qup6_spi_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup6_spi_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup6_i2c_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup6_i2c_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup5_spi_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup5_spi_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup5_i2c_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup5_i2c_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup4_spi_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup4_spi_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup4_i2c_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup4_i2c_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup3_spi_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup3_spi_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup3_i2c_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup3_i2c_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup2_spi_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup2_spi_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup2_i2c_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup2_i2c_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup1_spi_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup1_spi_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup1_i2c_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup1_i2c_apps_clk 0 0 0 50000000 0 0 50000 N
sleep_clk 2 2 0 32768 0 0 50000 Y
gcc_sleep_clk_src 3 3 0 32768 0 0 50000 Y
gcc_usb1_sleep_clk 1 1 0 32768 0 0 50000 Y
gcc_usb0_sleep_clk 1 1 0 32768 0 0 50000 Y
pcie1_pipe_clk_src 0 0 0 0 0 0 50000 Y
gcc_pcie1_pipe_clk 0 0 0 0 0 0 50000 N
pcie0_pipe_clk_src 0 0 0 0 0 0 50000 Y
gcc_pcie0_pipe_clk 0 0 0 0 0 0 50000 N
so I have been doing some tests using the mdio utility ...
mdio
90000.mdio-1
fixed-0
mdio 9*
DEV PHY-ID LINK
0x00 0x00000000 down
0x08 0x00000000 down
0x10 0x004dd0b1 up
0x11 0x004dd0b1 down
0x12 0x004dd0b1 down
0x13 0x004dd0b1 up
0x14 0x004dd0b1 down
0x15 0x04820a05 down
listing the settings for the devices that are up - the aquantias are not showing i presume as I don't capabilities higher than 1000
mdio 9* 0x00
BMCR(0x00): 0x1040
flags: -reset -loopback +aneg-enable -power-down -isolate -aneg-restart
-collision-test
speed: 1000-half
BMSR(0x01): 0x6148
capabilities: -100-t4 +100-tx-f +100-tx-h -10-t-f -10-t-h -100-t2-f -100-t2-h
flags: +ext-status -aneg-complete -remote-fault +aneg-capable -link
-jabber -ext-register
ID(0x02/0x03): 00000000
ESTATUS(0x0F): 0000
capabilities: -1000-x-f -1000-x-h -1000-t-f -1000-t-h
root@dragonfly-qnap:~# mdio 9* 0x13
BMCR(0x00): 0x1040
flags: -reset -loopback +aneg-enable -power-down -isolate -aneg-restart
-collision-test
speed: 1000-half
BMSR(0x01): 0x796d
capabilities: -100-t4 +100-tx-f +100-tx-h +10-t-f +10-t-h -100-t2-f -100-t2-h
flags: +ext-status +aneg-complete -remote-fault +aneg-capable +link
-jabber +ext-register
ID(0x02/0x03): 0x004dd0b1
ESTATUS(0x0F): 0x2000
capabilities: -1000-x-f -1000-x-h +1000-t-f -1000-t-h
mdio is reporting speed is half " speed: 1000-half" ... is this correct? ethtool shows 1000b/s
Settings for lan1:
Supported ports: [ TP MII ]
Supported link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Full
Supported pause frame use: Symmetric Receive-only
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Full
Advertised pause frame use: Symmetric Receive-only
Advertised auto-negotiation: Yes
Advertised FEC modes: Not reported
Link partner advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Full
Link partner advertised pause frame use: Symmetric Receive-only
Link partner advertised auto-negotiation: Yes
Link partner advertised FEC modes: Not reported
Speed: 1000Mb/s
Duplex: Full
Auto-negotiation: on
master-slave cfg: preferred master
master-slave status: master
Port: MII
PHYAD: 19
Transceiver: external
Link detected: yes
is this normal that mdio reports a different speed value than ethtool ? what takes precedence?
how about the aquantias why aren't they showing? under /sys/bus/mdio_bus I only can see Aquantia drivers ...
so I am confused !
0x0 and 0x8 are the AQR-s, but they are C45 only so they dont have a C22 ID
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thank you ... is it normal that mdio is reporting 1000-half ?