Add support for ASUS RT-AX89X AX6000

For Developers
920

Technically this shouldn't be possible, if it's possible then it's too fragile. Simply put, the Asus stock .trx firmware is a lot bigger in size than my own compiled images although it is made differently.
And in the case the bootloop occurred I've just changed the DTS file (in my local repo) in my current working build. I cannot understand how that change changed the partition size.
I flashed it because at worst I expected that the 10G copper port wouldn't work with it either but I didn't expect it to bootloop.
And yes, when my own image became bigger I had to deselect the .trx image (in menuconfig) from building, otherwise the compile just failed. So there is a logic in the OpenWrt code that doesn't allow it to go over the specified safe size.
Does anyone know where they sell only single cables for UART connection? Because if I leave the cables connected permanently to the Asus UART header (I have cables permanently attached to my QNAP 301w) I'll be out of cables :slight_smile: .

Update
Answering my own questions - obviously the reason for the bootloop was the changed DTS. It was intended for dd-wrt and I shouldn't have rushed without carefully reviewing/comparing it first. I will try to modify it for OpenWrt.
The OpenWrt original one has

34 stdout-path = "serial0:115200n8";
35		/* We have to override root and ubi device passed by bootloader */
36		bootargs-append = " ubi.block=0,jffs2 root=/dev/ubiblock0_4";

while the modified one (for dd-wrt) has this

34 stdout-path = "serial0:115200n8";
35		/* We have to override root and ubi device passed by bootloader */
36		bootargs-append = " mitigations=off root=/dev/mtdblock15 rootfstype=squashfs";
921

What exactly is UBI_Cleaner.trx ?

922

@robimarko I've modified the DTS for OpenWrt (Attention - I've used the one for NSS build not the vanilla OpenWrt DTS as dd-wrt uses NSS).
I've added the changes made by @BrainSlayer for B1 revision for dd-wrt.
I'm happy to announce that the 10g copper port is finally working on revision B1.
Here is the modified DTS file with working 10g copper port on my B1 revision (running NSS build).
As I'm really far from understanding the essence of those changes I just altered the file as carefully as I could.
@robimarko Please review the file (if it's correct) when you have time as I may have made a mistake somewhere.
The bellow DTS should work with both B1 and B2 revisions but I only tested it on my B1 revision with NSS support. For vanilla OpenWrt it will be different as there is no NSS support in it and it may not work properly.

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2024, Robert Marko <robimarko@gmail.com> */

/dts-v1/;

#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-nss.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>

/ {
	model = "Asus RT-AX89X";
	compatible = "asus,rt-ax89x", "qcom,ipq8074";

	aliases {
		serial0 = &blsp1_uart5;
		mdio-gpio0 = &mdio1;
		ethernet0 = &dp1;
		ethernet1 = &dp2;
		ethernet2 = &dp3;
		ethernet3 = &dp4;
		ethernet4 = &dp5_syn;
		ethernet5 = &dp6_syn;
		led-boot = &led_pwr;
		led-failsafe = &led_pwr;
		led-running = &led_pwr;
		led-upgrade = &led_pwr;
	};

	chosen {
		stdout-path = "serial0:115200n8";
		/* We have to override root and ubi device passed by bootloader */
		bootargs-append = " ubi.block=0,jffs2 root=/dev/ubiblock0_4";
	};

	keys {
		compatible = "gpio-keys";
		pinctrl-0 = <&button_pins>;
		pinctrl-names = "default";

		wifi-button {
			label = "wifi";
			gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_WLAN>;
		};

		reset-button {
			label = "reset";
			gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_RESTART>;
		};

		wps-button {
			label = "wps";
			gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_WPS_BUTTON>;
		};

		led-button {
			label = "led";
			gpios = <&tlmm 25 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_LIGHTS_TOGGLE>;
		};
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-0 = <&led_pins>;
		pinctrl-names = "default";

		led_pwr: led-pwr {
			function = LED_FUNCTION_POWER;
			gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
			color = <LED_COLOR_ID_WHITE>;
		};

		led-2g {
			function = LED_FUNCTION_WLAN_2GHZ;
			gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
			color = <LED_COLOR_ID_WHITE>;
			linux,default-trigger = "phy0radio";
		};

		led-5g {
			function = LED_FUNCTION_WLAN_5GHZ;
			gpios = <&tlmm 19 GPIO_ACTIVE_HIGH>;
			color = <LED_COLOR_ID_WHITE>;
			linux,default-trigger = "phy1radio";
		};

		led-10g-copper {
			function = "aqr10g";
			gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>;
			color = <LED_COLOR_ID_WHITE>;
		};

		led-lan {
			function = LED_FUNCTION_LAN;
			gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
			color = <LED_COLOR_ID_WHITE>;
		};

		led-sfp {
			function = "sfp";
			gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>;
			color = <LED_COLOR_ID_WHITE>;
		};

		led-wan-red {
			function = LED_FUNCTION_WAN;
			gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>;
			color = <LED_COLOR_ID_RED>;
		};

		led-wan-white {
			function = LED_FUNCTION_WAN;
			gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
			color = <LED_COLOR_ID_WHITE>;
		};
	};

	gpio_fan: gpio-fan {
		compatible = "gpio-fan";
		pinctrl-0 = <&fan_pins>;
		pinctrl-names = "default";
		gpios = <&tlmm 64 GPIO_ACTIVE_HIGH
			 &tlmm 66 GPIO_ACTIVE_HIGH>;
		/*
		 * Not supported upstream, but good to document for
		 * future uses.
		 * It seems that Delta AFB0712VHB fan has its tacho
		 * output connected to GPIO 65.
		 */
		//rpm-gpios = <&tlmm 65 GPIO_ACTIVE_HIGH>;
		gpio-fan,speed-map = <    0 0
				          1600 1
				          1850 2
				          2100 3 >;
		#cooling-cells = <2>;
	};

	usb0_vbus: regulator-usb0-vbus {
		compatible = "regulator-fixed";
		regulator-name = "usb0_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&tlmm 30 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-boot-on;
	};

	usb1_vbus: regulator-usb1-vbus {
		compatible = "regulator-fixed";
		regulator-name = "usb1_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-boot-on;
	};
};

&cpu0_thermal {
	trips {
		cpu0_active: cpu-active {
			temperature = <70000>;
			hysteresis = <2000>;
			type = "active";
		};
	};

	cooling-maps {
		map2 {
			trip = <&cpu0_active>;
			cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
		};
	};
};

&cpu1_thermal {
	trips {
		cpu1_active: cpu-active {
			temperature = <70000>;
			hysteresis = <2000>;
			type = "active";
		};
	};

	cooling-maps {
		map2 {
			trip = <&cpu1_active>;
			cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
		};
	};
};

&cpu2_thermal {
	trips {
		cpu2_active: cpu-active {
			temperature = <70000>;
			hysteresis = <2000>;
			type = "active";
		};
	};

	cooling-maps {
		map2 {
			trip = <&cpu2_active>;
			cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
		};
	};
};

&cpu3_thermal {
	trips {
		cpu3_active: cpu-active {
			temperature = <70000>;
			hysteresis = <2000>;
			type = "active";
		};
	};

	cooling-maps {
		map2 {
			trip = <&cpu3_active>;
			cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
		};
	};
};

&cluster_thermal {
	trips {
		cluster_active: cluster-active {
			temperature = <70000>;
			hysteresis = <2000>;
			type = "active";
		};
	};

	cooling-maps {
		map2 {
			trip = <&cluster_active>;
			cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
		};
	};
};

&tlmm {
	button_pins: button-state {
		pins = "gpio25", "gpio26", "gpio34", "gpio61";
		function = "gpio";
		drive-strength = <8>;
		bias-pull-up;
	};

	i2c_pins: i2c-pins {
		pins = "gpio42", "gpio43";
		function = "blsp1_i2c";
		drive-strength = <8>;
		bias-disable;
	};

	mdio_pins: mdio-pins {
		mdc {
			pins = "gpio68";
			function = "mdc";
			drive-strength = <16>;
			bias-pull-up;
		};

		mdio {
			pins = "gpio69";
			function = "mdio";
			drive-strength = <16>;
			bias-pull-up;
		};
	};

	mdio_gpio_pins: mdio-gpio-pins {
		pins = "gpio54", "gpio56";
		function = "gpio";
		drive-strength = <8>;
		bias-pull-up;
	};

	uniphy_pins: uniphy_pinmux {
		mux {
			pins = "gpio60";
			function = "rx2";
			bias-disable;
		};

		sfp_tx_disable {
			pins = "gpio48";
			function = "gpio";
			drive-strength = <8>;
			bias-pull-down;
			output-low;
		};

		sfp_tx_fault {
			pins = "gpio62";
			function = "gpio";
			drive-strength = <8>;
			bias-pull-up;
			output-high;
		};

		sfp_mod_def0 {
			pins = "gpio46";
			function = "gpio";
			drive-strength = <8>;
			bias-pull-up;
		};
	};

	led_pins: led-state {
		power {
			pins = "gpio21";
			function = "gpio";
			drive-strength = <8>;
			bias-pull-up;
		};

		default_off {
			pins = "gpio18", "gpio19", "gpio20", "gpio47",
			       "gpio44", "gpio35", "gpio36";
			function = "gpio";
			drive-strength = <8>;
			bias-pull-down;
		};
	};

	fan_pins: fan-state {
		pins = "gpio64", "gpio66";
		function = "gpio";
		drive-strength = <8>;
		bias-disable;
		output-high;
	};
};

&blsp1_uart5 {
	status = "okay";
};

&prng {
	status = "okay";
};

&cryptobam {
	status = "okay";
};

&crypto {
	status = "okay";
};

&ssphy_0 {
	status = "okay";
};

&qusb_phy_0 {
	status = "okay";
	
	vdd-supply = <&usb0_vbus>;
};

&ssphy_1 {
	status = "okay";
};

&qusb_phy_1 {
	status = "okay";

	vdd-supply = <&usb1_vbus>;
};

&usb_0 {
	status = "okay";
};

&usb_1 {
	status = "okay";
};

&qpic_bam {
	status = "okay";
};

&qpic_nand {
	status = "okay";

	nand@0 {
		reg = <0>;
		nand-ecc-strength = <4>;
		nand-ecc-step-size = <512>;
		nand-bus-width = <8>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "0:sbl1";
				reg = <0x0 0x60000>;
				read-only;
			};

			partition@60000 {
				label = "0:mibib";
				reg = <0x00060000 0x40000>;
				read-only;
			};

			partition@a0000 {
				label = "0:qsee";
				reg = <0x000a0000 0x1e0000>;
				read-only;
			};

			partition@280000 {
				label = "0:devcfg";
				reg = <0x00280000 0x20000>;
				read-only;
			};

			partition@2a0000 {
				label = "0:apdp";
				reg = <0x002a0000 0x20000>;
				read-only;
			};

			partition@2c0000 {
				label = "0:rpm";
				reg = <0x002c0000 0x40000>;
				read-only;
			};

			partition@300000 {
				label = "0:cdt";
				reg = <0x00300000 0x20000>;
				read-only;
			};

			partition@320000 {
				label = "0:appsbl";
				reg = <0x00320000 0xc0000>;
				read-only;
			};

			partition@3e0000 {
				label = "0:appsblenv";
				reg = <0x003e0000 0x20000>;
			};

			partition@400000 {
				compatible = "linux,ubi";
				label = "UBI_DEV";
				reg = <0x00400000 0xfc00000>;
			};
		};
	};
};

&blsp1_i2c2 {
	status = "okay";
};

&mdio {
	status = "okay";

	pinctrl-0 = <&mdio_pins>;
	pinctrl-names = "default";
	reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>,
		      <&tlmm 55 GPIO_ACTIVE_LOW>;

	qca8337_0: ethernet-phy@0 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <0x0>;
	};

	qca8337_1: ethernet-phy@1 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <0x1>;
	};

	qca8337_2: ethernet-phy@2 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <0x2>;
	};

	qca8337_3: ethernet-phy@3 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <0x3>;
	};

	qca8337_4: ethernet-phy@4 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <0x4>;
	};

	/*
	 * Vendor bootloader has path for ethernet-phy@5 hardcoded
	 * and if its there it will delete the node, but since we
	 * need the QCA8035 for DSA lets fool the bootloader by using
	 * ethernet-phy@05 even though it causes DTC to print a warning.
	 */
	qca8035: ethernet-phy@05 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <0x5>;
	};

	qca8033: ethernet-phy@6 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <0x6>;
	};

	aqr107: ethernet-phy@7 {
		compatible ="ethernet-phy-ieee802.3-c45";
		reg = <7>;
	};

	ethernet-phy-package@8 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "qcom,qca8075-package";
		reg = <8>;

		qcom,package-mode = "qsgmii";

		qca8075_8: ethernet-phy@8 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0x8>;
		};

		qca8075_9: ethernet-phy@9 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0x9>;
		};

		qca8075_a: ethernet-phy@a {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0xa>;
		};

		qca8075_b: ethernet-phy@b {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0xb>;
		};
	};

	qca8337: switch@10 {
		compatible = "qca,qca8337";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x10>;

		ports {
			port@0 {
				reg = <0>;
				label = "cpu";
				ethernet = <&dp1>;
				phy-mode = "rgmii-rxid";
				phy-handle = <&qca8035>;
			};

			port@1 {
				reg = <1>;
				label = "lan7";
				phy-handle = <&qca8337_0>;
			};

			port@2 {
				reg = <2>;
				label = "lan6";
				phy-handle = <&qca8337_1>;
			};

			port@3 {
				reg = <3>;
				label = "lan5";
				phy-handle = <&qca8337_2>;
			};

			port@4 {
				reg = <4>;
				label = "lan4";
				phy-handle = <&qca8337_3>;
			};

			port@5 {
				reg = <5>;
				label = "lan3";
				phy-handle = <&qca8337_4>;
			};

			port@6 {
				reg = <6>;
				label = "lan8";
				phy-mode = "sgmii";
				phy-handle = <&qca8033>;
				managed = "in-band-status";
				qca,sgmii-enable-pll;
			};
		};
	};
};

&soc {
	/*
	 * This is techically incorrect and will cause a DTC warning as
	 * all nodes under a bus are supposed to have addresses as well
	 * but its required as bootloader has this path hardcoded in
	 * order to enable AQR113C on newer revisions.
	 */
	mdio1: mdio1 {
		compatible = "virtual,mdio-gpio";
		pinctrl-0 = <&mdio_gpio_pins>;
		pinctrl-names = "default";
		gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>,
			<&tlmm 54 GPIO_ACTIVE_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;

		/*
		 * PCB R5.00, AQR113C
		 * No idea why the bitbanged this one.
		 * @5 is wrong, but their bootloader has it hardcoded in
		 * order to dynamically enable the PHY for newer HW.
		 */
		aqr113c: ethernet-phy@5 {
			status = "disabled";
			compatible ="ethernet-phy-ieee802.3-c45";
			reg = <8>;
		};
	};
};

&switch {
	status = "okay";

	pinctrl-0 = <&uniphy_pins>;
	pinctrl-names = "default";

	switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT5 | ESS_PORT6)>; /* lan port bitmap */
	switch_wan_bmp = <ESS_PORT4>; /* wan port bitmap */
	switch_mac_mode = <MAC_MODE_QSGMII>; /* mac mode for uniphy instance0*/
	switch_mac_mode1 = <MAC_MODE_10GBASE_R>; /* mac mode for uniphy instance1*/
	switch_mac_mode2 = <MAC_MODE_USXGMII>; /* mac mode for uniphy instance2*/

	qcom,port_phyinfo {
		port@0 {
			port_id = <1>;
			phy_address = <0x8>;
		};
		port@1 {
			port_id = <2>;
			phy_address = <0x9>;
		};
		port@2 {
			port_id = <3>;
			phy_address = <0xa>;
		};
		port@3 {
			port_id = <4>;
			phy_address = <0xb>;
		};

		sfp: port@4 {
			port_id = <5>;
			phy_address = <30>;
			phy_i2c_address = <30>;
			phy-i2c-mode; /*i2c access phy */
			media-type = "sfp"; /* fiber mode */
			sfp_tx_dis_pin = <&tlmm 48 GPIO_ACTIVE_HIGH>;
			sfp_mod_present_pin = <&tlmm 46 GPIO_ACTIVE_LOW>;
		};

		/* PCB R1.00 ~ R4.20, AQR107/AQR113 A1,B0 */
		port@5 {
			port_id = <6>;
			phy_address = <7>;
			ethernet-phy-ieee802.3-c45;			
		};

		/* PCB R5.00, AQR113C */
		port@5_113c {
			status = "disabled";
			port_id = <6>;
			phy_address = <8>;
			ethernet-phy-ieee802.3-c45;
			mdiobus = <&mdio1>;
		};
	};
};

&edma {
	status = "okay";
};

&dp1 {
	status = "okay";
	phy-mode = "qsgmii";
	phy-handle = <&qca8075_8>;
	label = "switch";
};

&dp2 {
	status = "okay";
	phy-mode = "qsgmii";
	phy-handle = <&qca8075_9>;
	label = "lan2";
};

&dp3 {
	status = "okay";
	phy-mode = "qsgmii";
	phy-handle = <&qca8075_a>;
	label = "lan1";
};

&dp4 {
	status = "okay";
	phy-mode = "qsgmii";
	phy-handle = <&qca8075_b>;
	label = "wan";
};

&dp5_syn {
	status = "okay";
	phy-handle = <&sfp>;
	label = "10g-sfp";
};

&dp6 {
	status = "okay";
	phy-handle = <&aqr107>;
	label = "10g-copper";
	reg = <0x3a007000 0x3fff>;
	qcom,mactype = <1>;
};

&dp6_syn {
	status = "okay";
	phy-handle = <&aqr113c>;
	label = "10g-copper";
};

&wifi {
	status = "okay";
	qcom,ath11k-calibration-variant = "Asus-RT-AX89X";
};

I've tried 2.5G and 10G connection. Both work OK and I tried the 10g-copper port as WAN and LAN port. 10g LED works too.
Thanks @BrainSlayer for providing the settings for the 10g copper port for B1 revision.
I have the same router that is revision B2 but I haven't tried my new build on it as I don't want to open it as the other one that is B1 revision.
Thanks guys and hope everyone that has B1 revision will be able to use it's full throughput.
Cheers!

1 Like
923

cool. i was never able to test it. i just took the information from the gpl sources from asus and guessed how to make it. but if it works it should work on all revisions now. i have a b2 and it works on it. regarding your bootloop issue. do not use the dd-wrt commandlines. i have a different filesystem and partition handling. i also have a custom partition parser which make use of the original asus u-boot image format which is modified by asus. so it will only work with kernel modifications i made.

1 Like
924

Yeah, I've learnt that the hard way and because I wasn't careful but that's why I asked that question before trying to flash the build but no one responded and I took the risk.
I'm happy I didn't make bigger mess.
But I guess that's just another way to learn new things.
Thanks a lot once again.

Probably anyone else having B1 revision may want to try it as well.
Anyone to make a PR for it.

925

in the openwrt wiki is already a incaccurate comment linking to this thread for a modified dts. in fact this dts is a replacement since it supports b1 and b2 alltogether

btw. can you provide me 0x20 / 32 bytes from offset 0x4ff00 of the factory partition from the b1 model? this contains the board revision and version

1 Like
926

OK, I changed the info (hope it's more meaningful now) but I initially wrote it that way because I didn't have a confirmation form any other users/developers and I didn't test it on B2.

I'll need a little help with this. I don't know which one is the factory partition. Should I flash Asus stock firmware.

root@Asus:~# cat /proc/mtd
dev:    size   erasesize  name
mtd0: 00060000 00020000 "0:sbl1"
mtd1: 00040000 00020000 "0:mibib"
mtd2: 001e0000 00020000 "0:qsee"
mtd3: 00020000 00020000 "0:devcfg"
mtd4: 00020000 00020000 "0:apdp"
mtd5: 00040000 00020000 "0:rpm"
mtd6: 00020000 00020000 "0:cdt"
mtd7: 000c0000 00020000 "0:appsbl"
mtd8: 00020000 00020000 "0:appsblenv"
mtd9: 0fc00000 00020000 "UBI_DEV"
927

the UBI_DEV contains 3 partitions. Factory, Factory2 and linux. the linux partition is the boot partition. Factory etc. contain preconfigured data. so you need to attach ubi_dev first. if you killed that UBI_DEV for openwrt you are not able to use the original asus firmware anymore.

1 Like
928

Here it is

root@Asus:~# ubinfo /dev/ubi0
ubi0
Volumes count:                           6
Logical eraseblock size:                 126976 bytes, 124.0 KiB
Total amount of logical eraseblocks:     2016 (255983616 bytes, 244.1 MiB)
Amount of available logical eraseblocks: 0 (0 bytes)
Maximum count of volumes                 128
Count of bad physical eraseblocks:       0
Count of reserved physical eraseblocks:  40
Current maximum erase counter value:     2057
Minimum input/output unit size:          2048 bytes
Character device major/minor:            247:0
Present volumes:                         0, 1, 2, 3, 4, 5
root@Asus:~# ubinfo -a /dev/ubi0_0
Volume ID:   0 (on ubi0)
Type:        dynamic
Alignment:   1
Size:        3 LEBs (380928 bytes, 372.0 KiB)
State:       OK
Name:        nvram
Character device major/minor: 247:1
root@Asus:~# ubinfo -a /dev/ubi0_1
Volume ID:   1 (on ubi0)
Type:        dynamic
Alignment:   1
Size:        3 LEBs (380928 bytes, 372.0 KiB)
State:       OK
Name:        Factory
Character device major/minor: 247:2
root@Asus:~# ubinfo -a /dev/ubi0_2
Volume ID:   2 (on ubi0)
Type:        dynamic
Alignment:   1
Size:        3 LEBs (380928 bytes, 372.0 KiB)
State:       OK
Name:        Factory2
Character device major/minor: 247:3
root@Asus:~# ubinfo -a /dev/ubi0_3
Volume ID:   3 (on ubi0)
Type:        dynamic
Alignment:   1
Size:        45 LEBs (5713920 bytes, 5.4 MiB)
State:       OK
Name:        linux
Character device major/minor: 247:4
root@Asus:~# ubinfo -a /dev/ubi0_4
Volume ID:   4 (on ubi0)
Type:        dynamic
Alignment:   1
Size:        159 LEBs (20189184 bytes, 19.2 MiB)
State:       OK
Name:        jffs2
Character device major/minor: 247:5
root@Asus:~# ubinfo -a /dev/ubi0_5
Volume ID:   5 (on ubi0)
Type:        dynamic
Alignment:   1
Size:        1759 LEBs (223350784 bytes, 213.0 MiB)
State:       OK
Name:        rootfs_data
Character device major/minor: 247:6
root@Asus:~# dd if=/dev/ubi0_1 bs=1 skip=$((0x4FF00)) count=32 2>/dev/null | hexdump -C
00000000  42 ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  |B...............|
00000010  32 2e 30 00 00 00 00 00  32 30 32 31 30 32 32 30  |2.0.....20210220|
00000020
root@Asus:~# dd if=/dev/ubi0_2 bs=1 skip=$((0x4FF00)) count=32 2>/dev/null | hexdump -C
00000000  42 ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  |B...............|
00000010  32 2e 30 00 00 00 00 00  32 30 32 31 30 32 32 30  |2.0.....20210220|
00000020

Is it OK. There are 6 partitions.

I hope UBI_DEV is intact as there is some data in it - 2.0.....20210220.
I don't know exactly what could have killed the UBI_DEV as I only flashed OpenWrt the regular way. Although I don't need the Asus firmware what important data those partitions contain that in case of being deleted prevents from using the Asus firmware?
I've made backup of the partitions using dd.

dd if=/dev/mtd0 of=/tmp/mtd0_backup.img bs=64k
dd if=/dev/mtd1 of=/tmp/mtd1_backup.img bs=64k
dd if=/dev/mtd2 of=/tmp/mtd2_backup.img bs=64k
dd if=/dev/mtd3 of=/tmp/mtd3_backup.img bs=64k
dd if=/dev/mtd4 of=/tmp/mtd4_backup.img bs=64k
dd if=/dev/mtd5 of=/tmp/mtd5_backup.img bs=64k
dd if=/dev/mtd6 of=/tmp/mtd6_backup.img bs=64k
dd if=/dev/mtd7 of=/tmp/mtd7_backup.img bs=64k
dd if=/dev/mtd8 of=/tmp/mtd8_backup.img bs=64k
dd if=/dev/mtd9 of=/tmp/mtd9_backup.img bs=64k
929

Bootloader, which started by parent Bootloader:
https://github.com/openwrt-xiaomi/openwrt/commit/fc963ffa39ad42f26252cd565332db2c12dc8d54#diff-75ca6b134415dfb1aaa9878f4dc62282eb48b5cbe4b4627d14afaf1a7cdd2502R299-R309

1 Like
930

dont know how you run openwrt. normally the ubi_dev contains the factory partitions with some voodoo configs and the linux partition which is split into kernel and rootfs. in dd-wrt i implemented this all just to boot in the same way as asus did. so for me it present. if you just boot initramfs it wont belong to you of course. but splitting here is not easy since the uimage format of asus is different from standard. i had to modify the ubi code to get it working correct for me with all the special dd-wrt things like nvram. but okay. i see in your factory data that the board rev is "B" . this is the B1. the B2 as printed on the sticker contains C and als version 2.1. i just wanted to know whats in the older devices which i dont have

1 Like
931

If anyone wants me to try anything else while I still test it and have an UART connection, please let me know, so I can do it.

Do LED and WLAN buttons work for you guys? When I press any of them nothing happens - the LEDs continue to work and WiFI doesn't turn off/on.

932

I can test it on revision B2 if you share the build or some instructions about how to do it.

933

Do you have an UART connection. I don't want to cause any trouble to you and your device. It's just regular sysupgrade if you already run OpenWrt.
If you want to try it I will be glad to share the build with you.

934

I have the cables and can do it if required. Hopefully not :D. I have already the official build. So changing the build shouldn't be an issue. If you can share will be awesome. Thank you!

935

10g copper port is working on b2 revision too. Led is working too. Checked with 2.5G connection.

2 Likes
936

Nice and thanks for testing it on B2.
Do LED and WLAN buttons work for you?

937

Leds are ok. Lan led is not configured by default but works too. Buttons do not work.

1 Like