Hi folks,
got the following error on uboot-lanitq while compiling from scratch.
Downgraded from gawk-5.4.0-1 to gawk 5.3.2-1 and it compiles again.
awk:26: error: ? * + or {interval} not preceded by valid subpattern: /* Clear access error log registers */
ERROR: package/boot/uboot-lantiq failed to build (build variant: bthomehubv5a_ram).
disable all ram version also works if anyone runs into it.
not sure if the bug report has to be made towards u-boot or openwrt.
to use the old matcher for this part.
gawk-5.4.0 changelog:
- This release now uses Mike Haertel's MinRX regular expression matcher
as the default regexp engine. The old regex and dfa engines are still
available. More detail is available in the manual, and in the file
README_d/README.matchers. At the very least, read that file!
If upgrading gawk broke things that were working, I'd suggest that the initial bug report should likely go to gawk. Although the correctness of the regex subpattern should perhaps be checked first, maybe it is an invalid regex pattern that should be fixed in whichever project hosts it (uboot / OpenWrt).
As with all open source projects though, a "bug report" is less appreciated than both a bug report and a PR / patch which fixes up the issue.
As written, it is not a gawk bug, but the old regex engine can be still used until it gets removed.
instead of “make” use “GAWK_GNU_MATCHERS=1 make”
This will work for some time, maybe the code gets dropped anyway.
It affects all versions, with the old u-boot (uboot) from 2013.
PR may follow when I remember how to do it.
package/boot/uboot-lantiq/patches/0118-fix-gawk-5.4-regex-compat.patch
--- a/tools/lantiq_ram_init_uart.awk
+++ b/tools/lantiq_ram_init_uart.awk
@@ -23,45 +23,45 @@ function print_header()
function mc_danube_prologue()
{
/* Clear access error log registers /
+# / Clear access error log registers */
print "0xbf800010", "0x0"
print "0xbf800020", "0x0"
/* Enable DDR and SRAM module in memory controller /
+# / Enable DDR and SRAM module in memory controller */
print "0xbf800060", "0x5"
/* Clear start bit of DDR memory controller /
+# / Clear start bit of DDR memory controller */
print "0xbf801030", "0x0"
}
function mc_ar9_prologue()
{
/* Clear access error log registers /
+# / Clear access error log registers */
print "0xbf800010", "0x0"
print "0xbf800020", "0x0"
/* Enable FPI, DDR and SRAM module in memory controller /
+# / Enable FPI, DDR and SRAM module in memory controller */
print "0xbf800060", "0xD"
/* Clear start bit of DDR memory controller /
+# / Clear start bit of DDR memory controller */
print "0xbf801030", "0x0"
}
function mc_ddr1_epilogue()
{
/* Set start bit of DDR memory controller /
+# / Set start bit of DDR memory controller */
print "0xbf801030", "0x100"
}
function mc_ddr2_prologue()
{
/* Put memory controller in inactive mode /
+# / Put memory controller in inactive mode */
print "0xbf401070", "0x0"
}
function mc_ddr2_epilogue(mc_ccr07_value)
{
/* Put memory controller in active mode /
+# / Put memory controller in active mode */
mc_ccr07_value = or(mc_ccr07_value, 0x100)
printf("0xbf401070 0x%x\n", mc_ccr07_value)
}
@@ -92,13 +92,14 @@ BEGIN {
}
/^#define/ {
/* CCR07 contains MC enable bit and must not be set here */
if (tolower($2) == "mc_ccr07_value")
+# /* CCR07 contains MC enable bit and must not be set here */
if (tolower($2) == "mc_ccr07_value") {
mc_ccr07_value = strtonum($3)
if (tolower($2) == "mc_dc03_value")
/* CCR07 contains MC enable bit and must not be set here */
else
} else if (tolower($2) == "mc_dc03_value") {
+# /* CCR07 contains MC enable bit and must not be set here */
} else {
printf("0x%x %s\n", reg_base, tolower($3))
}
reg_base += 0x10
}
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